Merge branch 'redist_slack' of gitlab.com:SymbioticEDA/nextpnr into redist_slack

3 files changed, 92 insertions, 45 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 76ce6a39..bdfb13fe 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -204,7 +204,7 @@ Arch::Arch(ArchArgs args) : args(args)
 
 // -----------------------------------------------------------------------
 
-std::string Arch::getChipName()
+std::string Arch::getChipName() const
 {
 #ifdef ICE40_HX1K_ONLY
     if (args.type == ArchArgs::HX1K) {
@@ -311,9 +311,23 @@ PortType Arch::getBelPinType(BelId bel, PortPin pin) const
     int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
     const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
 
-    for (int i = 0; i < num_bel_wires; i++)
-        if (bel_wires[i].port == pin)
-            return PortType(bel_wires[i].type);
+    if (num_bel_wires < 7) {
+        for (int i = 0; i < num_bel_wires; i++) {
+            if (bel_wires[i].port == pin)
+                return PortType(bel_wires[i].type);
+        }
+    } else {
+        int b = 0, e = num_bel_wires-1;
+        while (b <= e) {
+            int i = (b+e) / 2;
+            if (bel_wires[i].port == pin)
+                return PortType(bel_wires[i].type);
+            if (bel_wires[i].port > pin)
+                e = i-1;
+            else
+                b = i+1;
+        }
+    }
 
     return PORT_INOUT;
 }
@@ -327,10 +341,25 @@ WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
     int num_bel_wires = chip_info->bel_data[bel.index].num_bel_wires;
     const BelWirePOD *bel_wires = chip_info->bel_data[bel.index].bel_wires.get();
 
-    for (int i = 0; i < num_bel_wires; i++) {
-        if (bel_wires[i].port == pin) {
-            ret.index = bel_wires[i].wire_index;
-            break;
+    if (num_bel_wires < 7) {
+        for (int i = 0; i < num_bel_wires; i++) {
+            if (bel_wires[i].port == pin) {
+                ret.index = bel_wires[i].wire_index;
+                break;
+            }
+        }
+    } else {
+        int b = 0, e = num_bel_wires-1;
+        while (b <= e) {
+            int i = (b+e) / 2;
+            if (bel_wires[i].port == pin) {
+                ret.index = bel_wires[i].wire_index;
+                break;
+            }
+            if (bel_wires[i].port > pin)
+                e = i-1;
+            else
+                b = i+1;
         }
     }
 
@@ -602,6 +631,11 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
     int xd = sink_loc.x - driver_loc.x, yd = sink_loc.y - driver_loc.y;
     int xscale = 120, yscale = 120, offset = 0;
 
+    // if (chip_info->wire_data[src.index].type == WIRE_TYPE_SP4_VERT) {
+    //     yd = yd < -4 ? yd + 4 : (yd < 0 ? 0 : yd);
+    //     offset = 500;
+    // }
+
     if (driver.port == id_o) offset += 330;
     if (sink.port == id_i0 || sink.port == id_i1 || sink.port == id_i2 || sink.port == id_i3) offset += 260;
 
diff --git a/ice40/arch.h b/ice40/arch.h
index a4d148e5..92698b4d 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -44,9 +44,9 @@ template <typename T> struct RelPtr
 };
 
 NPNR_PACKED_STRUCT(struct BelWirePOD {
-    int32_t wire_index;
     PortPin port;
     int32_t type;
+    int32_t wire_index;
 });
 
 NPNR_PACKED_STRUCT(struct BelInfoPOD {
@@ -365,7 +365,7 @@ struct Arch : BaseCtx
     ArchArgs args;
     Arch(ArchArgs args);
 
-    std::string getChipName();
+    std::string getChipName() const;
 
     IdString archId() const { return id("ice40"); }
     IdString archArgsToId(ArchArgs args) const;
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 3ef58185..97ccbe48 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -214,56 +214,71 @@ def wire_type(name):
         assert 0
     return wt
 
-def pipdelay(src, dst, db):
+def pipdelay(src_idx, dst_idx, db):
     if db is None:
         return 0
 
-    src = wire_names_r[src]
-    dst = wire_names_r[dst]
+    src = wire_names_r[src_idx]
+    dst = wire_names_r[dst_idx]
     src_type = wire_type(src[2])
     dst_type = wire_type(dst[2])
 
-    if dst[2].startswith("local_"):
-        return db["LocalMux.I.O"]
+    if dst[2].startswith("sp4_") or dst[2].startswith("span4_"):
+        if src[2].startswith("sp12_") or src[2].startswith("span12_"):
+            return db["Sp12to4.I.O"]
+
+        if src[2].startswith("span4_"):
+            return db["IoSpan4Mux.I.O"]
+
+        if dst[2].startswith("sp4_h_"):
+            return db["Span4Mux_h4.I.O"]
+        else:
+            return db["Span4Mux_v4.I.O"]
 
-    if src_type == "LOCAL" and dst_type == "LOCAL":
-       return 250
+    if dst[2].startswith("sp12_") or dst[2].startswith("span12_"):
+        if dst[2].startswith("sp12_h_"):
+            return db["Span12Mux_h12.I.O"]
+        else:
+            return db["Span12Mux_v12.I.O"]
 
-    if src_type == "GLOBAL" and dst_type == "LOCAL":
-       return 400
+    if dst[2] in ("fabout", "clk"):
+        return 0 # FIXME?
 
-    # Local -> Span
+    if src[2].startswith("glb_netwk_") and dst[2].startswith("glb2local_"):
+        return 0 # FIXME?
 
-    if src_type == "LOCAL" and dst_type in ("SP4_HORZ", "SP4_VERT"):
-       return 350
+    if dst[2] == "carry_in_mux":
+        return db["ICE_CARRY_IN_MUX.carryinitin.carryinitout"]
 
-    if src_type == "LOCAL" and dst_type in ("SP12_HORZ", "SP12_VERT"):
-       return 500
+    if dst[2] in ("lutff_global/clk", "io_global/inclk", "io_global/outclk", "ram/RCLK", "ram/WCLK"):
+        return db["ClkMux.I.O"]
 
-    # Span -> Local
+    if dst[2] in ("lutff_global/s_r", "io_global/latch", "ram/RE", "ram/WE"):
+        return db["SRMux.I.O"]
 
-    if src_type in ("SP4_HORZ", "SP4_VERT", "SP12_HORZ", "SP12_VERT") and dst_type == "LOCAL":
-       return 300
+    if dst[2] in ("lutff_global/cen", "io_global/cen", "ram/RCLKE", "ram/WCLKE"):
+        return db["CEMux.I.O"]
 
-    # Span -> Span
+    if dst[2].startswith("local_"):
+        return db["LocalMux.I.O"]
 
-    if src_type in ("SP12_HORZ", "SP12_VERT") and dst_type in ("SP12_HORZ", "SP12_VERT"):
-       return 450
+    if src[2].startswith("local_") and dst[2] in ("io_0/D_OUT_0", "io_0/D_OUT_1", "io_0/OUT_ENB", "io_1/D_OUT_0", "io_1/D_OUT_1", "io_1/OUT_ENB"):
+        return db["IoInMux.I.O"]
 
-    if src_type in ("SP4_HORZ", "SP4_VERT") and dst_type in ("SP4_HORZ", "SP4_VERT"):
-       return 300
+    if re.match(r"lutff_\d+/in_\d+", dst[2]):
+        return db["InMux.I.O"]
 
-    if src_type in ("SP12_HORZ", "SP12_VERT") and dst_type in ("SP4_HORZ", "SP4_VERT"):
-       return 380
+    if re.match(r"ram/(MASK|RADDR|WADDR|WDATA)_", dst[2]):
+        return db["InMux.I.O"]
 
-    # print(src, dst, src_type, dst_type, file=sys.stderr)
+    print(src, dst, src_idx, dst_idx, src_type, dst_type, file=sys.stderr)
     assert 0
 
-def wiredelay(wire, db):
+def wiredelay(wire_idx, db):
     if db is None:
         return 0
 
-    wire = wire_names_r[wire]
+    wire = wire_names_r[wire_idx]
     wtype = wire_type(wire[2])
 
     # FIXME
@@ -492,13 +507,13 @@ def add_bel_input(bel, wire, port):
     if wire not in wire_belports:
         wire_belports[wire] = set()
     wire_belports[wire].add((bel, port))
-    bel_wires[bel].append((wire, port, 0))
+    bel_wires[bel].append((portpins[port], 0, wire))
 
 def add_bel_output(bel, wire, port):
     if wire not in wire_belports:
         wire_belports[wire] = set()
     wire_belports[wire].add((bel, port))
-    bel_wires[bel].append((wire, port, 1))
+    bel_wires[bel].append((portpins[port], 1, wire))
 
 def add_bel_lc(x, y, z):
     bel = len(bel_name)
@@ -759,14 +774,12 @@ bba.post('NEXTPNR_NAMESPACE_END')
 bba.push("chipdb_blob_%s" % dev_name)
 bba.r("chip_info_%s" % dev_name, "chip_info")
 
-index = 0
 for bel in range(len(bel_name)):
     bba.l("bel_wires_%d" % bel, "BelWirePOD")
-    for i in range(len(bel_wires[bel])):
-        bba.u32(bel_wires[bel][i][0], "wire_index")
-        bba.u32(portpins[bel_wires[bel][i][1]], "port")
-        bba.u32(bel_wires[bel][i][2], "type")
-        index += 1
+    for data in sorted(bel_wires[bel]):
+        bba.u32(data[0], "port")
+        bba.u32(data[1], "type")
+        bba.u32(data[2], "wire_index")
 
 bba.l("bel_data_%s" % dev_name, "BelInfoPOD")
 for bel in range(len(bel_name)):