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| author | Sergiusz Bazanski <q3k@q3k.org> | 2018-06-20 20:28:48 +0100 |
|---|---|---|
| committer | Sergiusz Bazanski <q3k@q3k.org> | 2018-06-20 20:28:48 +0100 |
| commit | 4e480a9a61e62c5e335d8736afa72e108ebaedfb (patch) | |
| tree | 300cbbdd30f4b389e11c60ebb5ee4c21bda30e30 /ice40 | |
| parent | 71121b439b0b4546eec0cd405627622e5cae029a (diff) | |
| download | nextpnr-4e480a9a61e62c5e335d8736afa72e108ebaedfb.tar.gz nextpnr-4e480a9a61e62c5e335d8736afa72e108ebaedfb.tar.bz2 nextpnr-4e480a9a61e62c5e335d8736afa72e108ebaedfb.zip | |
chipdb.py style fix
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/chipdb.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py index fe25c1f1..37606b54 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -37,7 +37,7 @@ wire_names_r = dict() wire_xy = dict() num_tile_types = 5 -tile_sizes = {_: (0, 0) for _ in range(num_tile_types)} +tile_sizes = {i: (0, 0) for i in range(num_tile_types)} tile_bits = [[] for _ in range(num_tile_types)] cbit_re = re.compile(r'B(\d+)\[(\d+)\]') |