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| author | Clifford Wolf <clifford@clifford.at> | 2018-06-20 12:58:08 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-06-20 12:58:08 +0200 |
| commit | 37f7802c6cfb9d9612e595c9914704c5403db9df (patch) | |
| tree | 491fcb456e88524adec3eda9be1b918080d2c834 /ice40 | |
| parent | 7c3593ea5acef05546be8835e25cf5e4b18549ee (diff) | |
| parent | 6d2f058f678761e90fc451af48f4e0ed0f504603 (diff) | |
| download | nextpnr-37f7802c6cfb9d9612e595c9914704c5403db9df.tar.gz nextpnr-37f7802c6cfb9d9612e595c9914704c5403db9df.tar.bz2 nextpnr-37f7802c6cfb9d9612e595c9914704c5403db9df.zip | |
Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr
Diffstat (limited to 'ice40')
| -rw-r--r-- | ice40/arch.cc | 21 | ||||
| -rw-r--r-- | ice40/arch.h | 11 |
2 files changed, 32 insertions, 0 deletions
diff --git a/ice40/arch.cc b/ice40/arch.cc index 3dcd9cb0..0fb02758 100644 --- a/ice40/arch.cc +++ b/ice40/arch.cc @@ -415,4 +415,25 @@ std::vector<GraphicElement> Arch::getPipGraphics(PipId pip) const return ret; } +// ----------------------------------------------------------------------- + +bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, + IdString toPort, delay_t &delay) const +{ + // TODO + return false; +} + +IdString Arch::getPortClock(const CellInfo *cell, IdString port) const +{ + // TODO + return IdString(); +} + +bool Arch::isClockPort(const CellInfo *cell, IdString port) const +{ + // TODO + return false; +} + NEXTPNR_NAMESPACE_END diff --git a/ice40/arch.h b/ice40/arch.h index d9631c11..85fb9fc0 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -770,6 +770,17 @@ struct Arch : BaseCtx std::unordered_set<BelId> belGraphicsReload; std::unordered_set<WireId> wireGraphicsReload; std::unordered_set<PipId> pipGraphicsReload; + + // ------------------------------------------------- + + // Get the delay through a cell from one port to another, returning false + // if no path exists + bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, + delay_t &delay) const; + // Get the associated clock to a port, or empty if the port is combinational + IdString getPortClock(const CellInfo *cell, IdString port) const; + // Return true if a port is a clock + bool isClockPort(const CellInfo *cell, IdString port) const; }; NEXTPNR_NAMESPACE_END |