Major Property improvements for common and iCE40

Signed-off-by: David Shah <dave@ds0.me>

8 files changed, 169 insertions, 161 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 0b1d280c..cc50cb68 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -689,7 +689,7 @@ bool Arch::place()
         tocfg.cellTypes.insert(id_ICESTORM_LC);
         retVal = timing_opt(getCtx(), tocfg);
     }
-    getCtx()->settings[getCtx()->id("place")] = "1";
+    getCtx()->settings[getCtx()->id("place")] = 1;
     archInfoToAttributes();
     return retVal;
 }
@@ -697,7 +697,7 @@ bool Arch::place()
 bool Arch::route()
 {
     bool retVal = router1(getCtx(), Router1Cfg(getCtx()));
-    getCtx()->settings[getCtx()->id("route")] = "1";
+    getCtx()->settings[getCtx()->id("route")] = 1;
     archInfoToAttributes();
     return retVal;
 }
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 7632b443..7149f127 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -23,6 +23,7 @@
 #include <vector>
 #include "cells.h"
 #include "log.h"
+#include "util.h"
 
 NEXTPNR_NAMESPACE_BEGIN
 
@@ -98,12 +99,15 @@ void set_ie_bit_logical(const Context *ctx, const TileInfoPOD &ti, std::vector<s
     }
 }
 
-int get_param_or_def(const CellInfo *cell, const IdString param, int defval = 0)
+int get_param_or_def(const Context *ctx, const CellInfo *cell, const IdString param, int defval = 0)
 {
     auto found = cell->params.find(param);
-    if (found != cell->params.end())
-        return std::stoi(found->second);
-    else
+    if (found != cell->params.end()) {
+        if (found->second.is_string)
+            log_error("expected numeric value for parameter '%s' on cell '%s'\n", param.c_str(ctx),
+                      cell->name.c_str(ctx));
+        return found->second.as_int64();
+    } else
         return defval;
 }
 
@@ -111,7 +115,7 @@ std::string get_param_str_or_def(const CellInfo *cell, const IdString param, std
 {
     auto found = cell->params.find(param);
     if (found != cell->params.end())
-        return found->second;
+        return found->second.as_string();
     else
         return defval;
 }
@@ -172,8 +176,8 @@ void configure_extra_cell(chipconfig_t &config, const Context *ctx, CellInfo *ce
         } else {
             int ival;
             try {
-                ival = get_param_or_def(cell, ctx->id(p.first), 0);
-            } catch (std::invalid_argument &e) {
+                ival = get_param_or_def(ctx, cell, ctx->id(p.first), 0);
+            } catch (std::exception &e) {
                 log_error("expected numeric value for parameter '%s' on cell '%s'\n", p.first.c_str(),
                           cell->name.c_str(ctx));
             }
@@ -419,12 +423,12 @@ void write_asc(const Context *ctx, std::ostream &out)
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y, z = beli.z;
             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_LOGIC];
-            unsigned lut_init = get_param_or_def(cell.second.get(), ctx->id("LUT_INIT"));
-            bool neg_clk = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK"));
-            bool dff_enable = get_param_or_def(cell.second.get(), ctx->id("DFF_ENABLE"));
-            bool async_sr = get_param_or_def(cell.second.get(), ctx->id("ASYNC_SR"));
-            bool set_noreset = get_param_or_def(cell.second.get(), ctx->id("SET_NORESET"));
-            bool carry_enable = get_param_or_def(cell.second.get(), ctx->id("CARRY_ENABLE"));
+            unsigned lut_init = get_param_or_def(ctx, cell.second.get(), ctx->id("LUT_INIT"));
+            bool neg_clk = get_param_or_def(ctx, cell.second.get(), ctx->id("NEG_CLK"));
+            bool dff_enable = get_param_or_def(ctx, cell.second.get(), ctx->id("DFF_ENABLE"));
+            bool async_sr = get_param_or_def(ctx, cell.second.get(), ctx->id("ASYNC_SR"));
+            bool set_noreset = get_param_or_def(ctx, cell.second.get(), ctx->id("SET_NORESET"));
+            bool carry_enable = get_param_or_def(ctx, cell.second.get(), ctx->id("CARRY_ENABLE"));
             std::vector<bool> lc(20, false);
 
             // Discover permutation
@@ -483,8 +487,8 @@ void write_asc(const Context *ctx, std::ostream &out)
             if (dff_enable)
                 set_config(ti, config.at(y).at(x), "NegClk", neg_clk);
 
-            bool carry_const = get_param_or_def(cell.second.get(), ctx->id("CIN_CONST"));
-            bool carry_set = get_param_or_def(cell.second.get(), ctx->id("CIN_SET"));
+            bool carry_const = get_param_or_def(ctx, cell.second.get(), ctx->id("CIN_CONST"));
+            bool carry_set = get_param_or_def(ctx, cell.second.get(), ctx->id("CIN_SET"));
             if (carry_const) {
                 if (!ctx->force)
                     NPNR_ASSERT(z == 0);
@@ -494,9 +498,9 @@ void write_asc(const Context *ctx, std::ostream &out)
             const BelInfoPOD &beli = ci.bel_data[bel.index];
             int x = beli.x, y = beli.y, z = beli.z;
             const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO];
-            unsigned pin_type = get_param_or_def(cell.second.get(), ctx->id("PIN_TYPE"));
-            bool neg_trigger = get_param_or_def(cell.second.get(), ctx->id("NEG_TRIGGER"));
-            bool pullup = get_param_or_def(cell.second.get(), ctx->id("PULLUP"));
+            unsigned pin_type = get_param_or_def(ctx, cell.second.get(), ctx->id("PIN_TYPE"));
+            bool neg_trigger = get_param_or_def(ctx, cell.second.get(), ctx->id("NEG_TRIGGER"));
+            bool pullup = get_param_or_def(ctx, cell.second.get(), ctx->id("PULLUP"));
             bool lvds = cell.second->ioInfo.lvds;
             bool used_by_pll_out = sb_io_used_by_pll_out.count(Loc(x, y, z)) > 0;
             bool used_by_pll_pad = sb_io_used_by_pll_pad.count(Loc(x, y, z)) > 0;
@@ -532,7 +536,7 @@ void write_asc(const Context *ctx, std::ostream &out)
                 if (ctx->args.type == ArchArgs::UP5K) {
                     std::string pullup_resistor = "100K";
                     if (cell.second->attrs.count(ctx->id("PULLUP_RESISTOR")))
-                        pullup_resistor = cell.second->attrs.at(ctx->id("PULLUP_RESISTOR"));
+                        pullup_resistor = cell.second->attrs.at(ctx->id("PULLUP_RESISTOR")).as_string();
                     NPNR_ASSERT(pullup_resistor == "100K" || pullup_resistor == "10K" || pullup_resistor == "6P8K" ||
                                 pullup_resistor == "3P3K");
                     if (iez == 0) {
@@ -599,10 +603,10 @@ void write_asc(const Context *ctx, std::ostream &out)
             if (!(ctx->args.type == ArchArgs::LP1K || ctx->args.type == ArchArgs::HX1K)) {
                 set_config(ti_ramb, config.at(y).at(x), "RamConfig.PowerUp", true);
             }
-            bool negclk_r = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK_R"));
-            bool negclk_w = get_param_or_def(cell.second.get(), ctx->id("NEG_CLK_W"));
-            int write_mode = get_param_or_def(cell.second.get(), ctx->id("WRITE_MODE"));
-            int read_mode = get_param_or_def(cell.second.get(), ctx->id("READ_MODE"));
+            bool negclk_r = get_param_or_def(ctx, cell.second.get(), ctx->id("NEG_CLK_R"));
+            bool negclk_w = get_param_or_def(ctx, cell.second.get(), ctx->id("NEG_CLK_W"));
+            int write_mode = get_param_or_def(ctx, cell.second.get(), ctx->id("WRITE_MODE"));
+            int read_mode = get_param_or_def(ctx, cell.second.get(), ctx->id("READ_MODE"));
             set_config(ti_ramb, config.at(y).at(x), "NegClk", negclk_w);
             set_config(ti_ramt, config.at(y + 1).at(x), "NegClk", negclk_r);
 
@@ -628,9 +632,9 @@ void write_asc(const Context *ctx, std::ostream &out)
             // No config needed
         } else if (cell.second->type == ctx->id("SB_I2C")) {
             bool sda_in_dly = !cell.second->attrs.count(ctx->id("SDA_INPUT_DELAYED")) ||
-                              std::stoi(cell.second->attrs[ctx->id("SDA_INPUT_DELAYED")]);
+                              cell.second->attrs[ctx->id("SDA_INPUT_DELAYED")].as_bool();
             bool sda_out_dly = !cell.second->attrs.count(ctx->id("SDA_OUTPUT_DELAYED")) ||
-                               std::stoi(cell.second->attrs[ctx->id("SDA_OUTPUT_DELAYED")]);
+                               cell.second->attrs[ctx->id("SDA_OUTPUT_DELAYED")].as_bool();
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SDA_INPUT_DELAYED", sda_in_dly,
                         "IpConfig.");
             set_ec_cbit(config, ctx, get_ec_config(ctx->chip_info, cell.second->bel), "SDA_OUTPUT_DELAYED", sda_out_dly,
@@ -861,10 +865,10 @@ void write_asc(const Context *ctx, std::ostream &out)
                 out << ".ram_data " << x << " " << y << std::endl;
                 for (int w = 0; w < 16; w++) {
                     std::vector<bool> bits(256);
-                    std::string init =
-                            get_param_str_or_def(cell.second.get(), ctx->id(std::string("INIT_") + get_hexdigit(w)));
-                    for (size_t i = 0; i < init.size(); i++) {
-                        bool val = (init.at((init.size() - 1) - i) == '1');
+                    Property init = get_or_default(cell.second->params, ctx->id(std::string("INIT_") + get_hexdigit(w)),
+                                                   Property(0, 256));
+                    for (size_t i = 0; i < init.str.size(); i++) {
+                        bool val = (init.str.at(i) == Property::State::S1);
                         bits.at(i) = val;
                     }
                     for (int i = bits.size() - 4; i >= 0; i -= 4) {
diff --git a/ice40/cells.cc b/ice40/cells.cc
index a2abcea4..c4e93d5b 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -43,14 +43,14 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
     }
     new_cell->type = type;
     if (type == ctx->id("ICESTORM_LC")) {
-        new_cell->params[ctx->id("LUT_INIT")] = "0";
-        new_cell->params[ctx->id("NEG_CLK")] = "0";
-        new_cell->params[ctx->id("CARRY_ENABLE")] = "0";
-        new_cell->params[ctx->id("DFF_ENABLE")] = "0";
-        new_cell->params[ctx->id("SET_NORESET")] = "0";
-        new_cell->params[ctx->id("ASYNC_SR")] = "0";
-        new_cell->params[ctx->id("CIN_CONST")] = "0";
-        new_cell->params[ctx->id("CIN_SET")] = "0";
+        new_cell->params[ctx->id("LUT_INIT")] = Property(0, 16);
+        new_cell->params[ctx->id("NEG_CLK")] = Property::State::S0;
+        new_cell->params[ctx->id("CARRY_ENABLE")] = Property::State::S0;
+        new_cell->params[ctx->id("DFF_ENABLE")] = Property::State::S0;
+        new_cell->params[ctx->id("SET_NORESET")] = Property::State::S0;
+        new_cell->params[ctx->id("ASYNC_SR")] = Property::State::S0;
+        new_cell->params[ctx->id("CIN_CONST")] = Property::State::S0;
+        new_cell->params[ctx->id("CIN_SET")] = Property::State::S0;
 
         add_port(ctx, new_cell.get(), "I0", PORT_IN);
         add_port(ctx, new_cell.get(), "I1", PORT_IN);
@@ -66,10 +66,10 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         add_port(ctx, new_cell.get(), "O", PORT_OUT);
         add_port(ctx, new_cell.get(), "COUT", PORT_OUT);
     } else if (type == ctx->id("SB_IO")) {
-        new_cell->params[ctx->id("PIN_TYPE")] = "0";
-        new_cell->params[ctx->id("PULLUP")] = "0";
-        new_cell->params[ctx->id("NEG_TRIGGER")] = "0";
-        new_cell->params[ctx->id("IOSTANDARD")] = "SB_LVCMOS";
+        new_cell->params[ctx->id("PIN_TYPE")] = Property(0, 6);
+        new_cell->params[ctx->id("PULLUP")] = Property::State::S0;
+        new_cell->params[ctx->id("NEG_TRIGGER")] = Property::State::S0;
+        new_cell->params[ctx->id("IOSTANDARD")] = Property("SB_LVCMOS");
 
         add_port(ctx, new_cell.get(), "PACKAGE_PIN", PORT_INOUT);
 
@@ -85,10 +85,10 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         add_port(ctx, new_cell.get(), "D_IN_0", PORT_OUT);
         add_port(ctx, new_cell.get(), "D_IN_1", PORT_OUT);
     } else if (type == ctx->id("ICESTORM_RAM")) {
-        new_cell->params[ctx->id("NEG_CLK_W")] = "0";
-        new_cell->params[ctx->id("NEG_CLK_R")] = "0";
-        new_cell->params[ctx->id("WRITE_MODE")] = "0";
-        new_cell->params[ctx->id("READ_MODE")] = "0";
+        new_cell->params[ctx->id("NEG_CLK_W")] = Property::State::S0;
+        new_cell->params[ctx->id("NEG_CLK_R")] = Property::State::S0;
+        new_cell->params[ctx->id("WRITE_MODE")] = Property::State::S0;
+        new_cell->params[ctx->id("READ_MODE")] = Property::State::S0;
 
         add_port(ctx, new_cell.get(), "RCLK", PORT_IN);
         add_port(ctx, new_cell.get(), "RCLKE", PORT_IN);
@@ -114,8 +114,8 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         add_port(ctx, new_cell.get(), "CLKLF", PORT_OUT);
         add_port(ctx, new_cell.get(), "CLKLF_FABRIC", PORT_OUT);
     } else if (type == ctx->id("ICESTORM_HFOSC")) {
-        new_cell->params[ctx->id("CLKHF_DIV")] = "0b00";
-        new_cell->params[ctx->id("TRIM_EN")] = "0b0";
+        new_cell->params[ctx->id("CLKHF_DIV")] = Property("0b00");
+        new_cell->params[ctx->id("TRIM_EN")] = Property("0b0");
 
         add_port(ctx, new_cell.get(), "CLKHFEN", PORT_IN);
         add_port(ctx, new_cell.get(), "CLKHFPU", PORT_IN);
@@ -145,30 +145,30 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
             add_port(ctx, new_cell.get(), "MASKWREN_" + std::to_string(i), PORT_IN);
         }
     } else if (type == ctx->id("ICESTORM_DSP")) {
-        new_cell->params[ctx->id("NEG_TRIGGER")] = "0";
-
-        new_cell->params[ctx->id("C_REG")] = "0";
-        new_cell->params[ctx->id("A_REG")] = "0";
-        new_cell->params[ctx->id("B_REG")] = "0";
-        new_cell->params[ctx->id("D_REG")] = "0";
-        new_cell->params[ctx->id("TOP_8x8_MULT_REG")] = "0";
-        new_cell->params[ctx->id("BOT_8x8_MULT_REG")] = "0";
-        new_cell->params[ctx->id("PIPELINE_16x16_MULT_REG1")] = "0";
-        new_cell->params[ctx->id("PIPELINE_16x16_MULT_REG2")] = "0";
-
-        new_cell->params[ctx->id("TOPOUTPUT_SELECT")] = "0";
-        new_cell->params[ctx->id("TOPADDSUB_LOWERINPUT")] = "0";
-        new_cell->params[ctx->id("TOPADDSUB_UPPERINPUT")] = "0";
-        new_cell->params[ctx->id("TOPADDSUB_CARRYSELECT")] = "0";
-
-        new_cell->params[ctx->id("BOTOUTPUT_SELECT")] = "0";
-        new_cell->params[ctx->id("BOTADDSUB_LOWERINPUT")] = "0";
-        new_cell->params[ctx->id("BOTADDSUB_UPPERINPUT")] = "0";
-        new_cell->params[ctx->id("BOTADDSUB_CARRYSELECT")] = "0";
-
-        new_cell->params[ctx->id("MODE_8x8")] = "0";
-        new_cell->params[ctx->id("A_SIGNED")] = "0";
-        new_cell->params[ctx->id("B_SIGNED")] = "0";
+        new_cell->params[ctx->id("NEG_TRIGGER")] = Property::State::S0;
+
+        new_cell->params[ctx->id("C_REG")] = Property::State::S0;
+        new_cell->params[ctx->id("A_REG")] = Property::State::S0;
+        new_cell->params[ctx->id("B_REG")] = Property::State::S0;
+        new_cell->params[ctx->id("D_REG")] = Property::State::S0;
+        new_cell->params[ctx->id("TOP_8x8_MULT_REG")] = Property::State::S0;
+        new_cell->params[ctx->id("BOT_8x8_MULT_REG")] = Property::State::S0;
+        new_cell->params[ctx->id("PIPELINE_16x16_MULT_REG1")] = Property::State::S0;
+        new_cell->params[ctx->id("PIPELINE_16x16_MULT_REG2")] = Property::State::S0;
+
+        new_cell->params[ctx->id("TOPOUTPUT_SELECT")] = Property(0, 2);
+        new_cell->params[ctx->id("TOPADDSUB_LOWERINPUT")] = Property(0, 2);
+        new_cell->params[ctx->id("TOPADDSUB_UPPERINPUT")] = Property::State::S0;
+        new_cell->params[ctx->id("TOPADDSUB_CARRYSELECT")] = Property(0, 2);
+
+        new_cell->params[ctx->id("BOTOUTPUT_SELECT")] = Property(0, 2);
+        new_cell->params[ctx->id("BOTADDSUB_LOWERINPUT")] = Property(0, 2);
+        new_cell->params[ctx->id("BOTADDSUB_UPPERINPUT")] = Property::State::S0;
+        new_cell->params[ctx->id("BOTADDSUB_CARRYSELECT")] = Property(0, 2);
+
+        new_cell->params[ctx->id("MODE_8x8")] = Property::State::S0;
+        new_cell->params[ctx->id("A_SIGNED")] = Property::State::S0;
+        new_cell->params[ctx->id("B_SIGNED")] = Property::State::S0;
 
         add_port(ctx, new_cell.get(), "CLK", PORT_IN);
         add_port(ctx, new_cell.get(), "CE", PORT_IN);
@@ -210,24 +210,24 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         add_port(ctx, new_cell.get(), "SIGNEXTOUT", PORT_OUT);
 
     } else if (type == ctx->id("ICESTORM_PLL")) {
-        new_cell->params[ctx->id("DELAY_ADJMODE_FB")] = "0";
-        new_cell->params[ctx->id("DELAY_ADJMODE_REL")] = "0";
+        new_cell->params[ctx->id("DELAY_ADJMODE_FB")] = Property::State::S0;
+        new_cell->params[ctx->id("DELAY_ADJMODE_REL")] = Property::State::S0;
 
-        new_cell->params[ctx->id("DIVF")] = "0";
-        new_cell->params[ctx->id("DIVQ")] = "0";
-        new_cell->params[ctx->id("DIVR")] = "0";
+        new_cell->params[ctx->id("DIVF")] = Property(0, 7);
+        new_cell->params[ctx->id("DIVQ")] = Property(0, 3);
+        new_cell->params[ctx->id("DIVR")] = Property(0, 4);
 
-        new_cell->params[ctx->id("FDA_FEEDBACK")] = "0";
-        new_cell->params[ctx->id("FDA_RELATIVE")] = "0";
-        new_cell->params[ctx->id("FEEDBACK_PATH")] = "1";
-        new_cell->params[ctx->id("FILTER_RANGE")] = "0";
+        new_cell->params[ctx->id("FDA_FEEDBACK")] = Property(0, 4);
+        new_cell->params[ctx->id("FDA_RELATIVE")] = Property(0, 4);
+        new_cell->params[ctx->id("FEEDBACK_PATH")] = Property(1, 3);
+        new_cell->params[ctx->id("FILTER_RANGE")] = Property(0, 3);
 
-        new_cell->params[ctx->id("PLLOUT_SELECT_A")] = "0";
-        new_cell->params[ctx->id("PLLOUT_SELECT_B")] = "0";
+        new_cell->params[ctx->id("PLLOUT_SELECT_A")] = Property(0, 2);
+        new_cell->params[ctx->id("PLLOUT_SELECT_B")] = Property(0, 2);
 
-        new_cell->params[ctx->id("PLLTYPE")] = "0";
-        new_cell->params[ctx->id("SHIFTREG_DIVMODE")] = "0";
-        new_cell->params[ctx->id("TEST_MODE")] = "0";
+        new_cell->params[ctx->id("PLLTYPE")] = Property(0, 3);
+        new_cell->params[ctx->id("SHIFTREG_DIVMODE")] = Property::State::S0;
+        new_cell->params[ctx->id("TEST_MODE")] = Property::State::S0;
 
         add_port(ctx, new_cell.get(), "BYPASS", PORT_IN);
         for (int i = 0; i < 8; i++)
@@ -247,10 +247,10 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         add_port(ctx, new_cell.get(), "PLLOUT_A_GLOBAL", PORT_OUT);
         add_port(ctx, new_cell.get(), "PLLOUT_B_GLOBAL", PORT_OUT);
     } else if (type == ctx->id("SB_RGBA_DRV")) {
-        new_cell->params[ctx->id("CURRENT_MODE")] = "0b0";
-        new_cell->params[ctx->id("RGB0_CURRENT")] = "0b000000";
-        new_cell->params[ctx->id("RGB1_CURRENT")] = "0b000000";
-        new_cell->params[ctx->id("RGB2_CURRENT")] = "0b000000";
+        new_cell->params[ctx->id("CURRENT_MODE")] = std::string("0b0");
+        new_cell->params[ctx->id("RGB0_CURRENT")] = std::string("0b000000");
+        new_cell->params[ctx->id("RGB1_CURRENT")] = std::string("0b000000");
+        new_cell->params[ctx->id("RGB2_CURRENT")] = std::string("0b000000");
 
         add_port(ctx, new_cell.get(), "CURREN", PORT_IN);
         add_port(ctx, new_cell.get(), "RGBLEDEN", PORT_IN);
@@ -264,9 +264,9 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         add_port(ctx, new_cell.get(), "EN", PORT_IN);
         add_port(ctx, new_cell.get(), "LEDPU", PORT_OUT);
     } else if (type == ctx->id("SB_RGB_DRV")) {
-        new_cell->params[ctx->id("RGB0_CURRENT")] = "0b000000";
-        new_cell->params[ctx->id("RGB1_CURRENT")] = "0b000000";
-        new_cell->params[ctx->id("RGB2_CURRENT")] = "0b000000";
+        new_cell->params[ctx->id("RGB0_CURRENT")] = std::string("0b000000");
+        new_cell->params[ctx->id("RGB1_CURRENT")] = std::string("0b000000");
+        new_cell->params[ctx->id("RGB2_CURRENT")] = std::string("0b000000");
 
         add_port(ctx, new_cell.get(), "RGBPU", PORT_IN);
         add_port(ctx, new_cell.get(), "RGBLEDEN", PORT_IN);
@@ -292,8 +292,8 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         add_port(ctx, new_cell.get(), "PWMOUT2", PORT_OUT);
         add_port(ctx, new_cell.get(), "LEDDON", PORT_OUT);
     } else if (type == ctx->id("SB_I2C")) {
-        new_cell->params[ctx->id("I2C_SLAVE_INIT_ADDR")] = "0b1111100001";
-        new_cell->params[ctx->id("BUS_ADDR74")] = "0b0001";
+        new_cell->params[ctx->id("I2C_SLAVE_INIT_ADDR")] = std::string("0b1111100001");
+        new_cell->params[ctx->id("BUS_ADDR74")] = std::string("0b0001");
         for (int i = 0; i < 8; i++) {
             add_port(ctx, new_cell.get(), "SBADRI" + std::to_string(i), PORT_IN);
             add_port(ctx, new_cell.get(), "SBDATI" + std::to_string(i), PORT_IN);
@@ -312,7 +312,7 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
         add_port(ctx, new_cell.get(), "SDAO", PORT_OUT);
         add_port(ctx, new_cell.get(), "SDAOE", PORT_OUT);
     } else if (type == ctx->id("SB_SPI")) {
-        new_cell->params[ctx->id("BUS_ADDR74")] = "0b0000";
+        new_cell->params[ctx->id("BUS_ADDR74")] = std::string("0b0000");
         for (int i = 0; i < 8; i++) {
             add_port(ctx, new_cell.get(), "SBADRI" + std::to_string(i), PORT_IN);
             add_port(ctx, new_cell.get(), "SBDATI" + std::to_string(i), PORT_IN);
@@ -346,29 +346,29 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
 
 void lut_to_lc(const Context *ctx, CellInfo *lut, CellInfo *lc, bool no_dff)
 {
-    lc->params[ctx->id("LUT_INIT")] = lut->params[ctx->id("LUT_INIT")];
+    lc->params[ctx->id("LUT_INIT")] = lut->params[ctx->id("LUT_INIT")].extract(0, 16, Property::State::S0);
     replace_port(lut, ctx->id("I0"), lc, ctx->id("I0"));
     replace_port(lut, ctx->id("I1"), lc, ctx->id("I1"));
     replace_port(lut, ctx->id("I2"), lc, ctx->id("I2"));
     replace_port(lut, ctx->id("I3"), lc, ctx->id("I3"));
     if (no_dff) {
         replace_port(lut, ctx->id("O"), lc, ctx->id("O"));
-        lc->params[ctx->id("DFF_ENABLE")] = "0";
+        lc->params[ctx->id("DFF_ENABLE")] = Property::State::S0;
     }
 }
 
 void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_lut)
 {
-    lc->params[ctx->id("DFF_ENABLE")] = "1";
+    lc->params[ctx->id("DFF_ENABLE")] = Property::State::S1;
     std::string config = dff->type.str(ctx).substr(6);
     auto citer = config.begin();
     replace_port(dff, ctx->id("C"), lc, ctx->id("CLK"));
 
     if (citer != config.end() && *citer == 'N') {
-        lc->params[ctx->id("NEG_CLK")] = "1";
+        lc->params[ctx->id("NEG_CLK")] = Property::State::S1;
         ++citer;
     } else {
-        lc->params[ctx->id("NEG_CLK")] = "0";
+        lc->params[ctx->id("NEG_CLK")] = Property::State::S0;
     }
 
     if (citer != config.end() && *citer == 'E') {
@@ -380,27 +380,27 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
         if ((config.end() - citer) >= 2) {
             char c = *(citer++);
             NPNR_ASSERT(c == 'S');
-            lc->params[ctx->id("ASYNC_SR")] = "0";
+            lc->params[ctx->id("ASYNC_SR")] = Property::State::S0;
         } else {
-            lc->params[ctx->id("ASYNC_SR")] = "1";
+            lc->params[ctx->id("ASYNC_SR")] = Property::State::S1;
         }
 
         if (*citer == 'S') {
             citer++;
             replace_port(dff, ctx->id("S"), lc, ctx->id("SR"));
-            lc->params[ctx->id("SET_NORESET")] = "1";
+            lc->params[ctx->id("SET_NORESET")] = Property::State::S1;
         } else {
             NPNR_ASSERT(*citer == 'R');
             citer++;
             replace_port(dff, ctx->id("R"), lc, ctx->id("SR"));
-            lc->params[ctx->id("SET_NORESET")] = "0";
+            lc->params[ctx->id("SET_NORESET")] = Property::State::S0;
         }
     }
 
     NPNR_ASSERT(citer == config.end());
 
     if (pass_thru_lut) {
-        lc->params[ctx->id("LUT_INIT")] = "2";
+        lc->params[ctx->id("LUT_INIT")] = Property(2, 16);
         replace_port(dff, ctx->id("D"), lc, ctx->id("I0"));
     }
 
@@ -410,17 +410,17 @@ void dff_to_lc(const Context *ctx, CellInfo *dff, CellInfo *lc, bool pass_thru_l
 void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set<IdString> &todelete_cells)
 {
     if (nxio->type == ctx->id("$nextpnr_ibuf")) {
-        sbio->params[ctx->id("PIN_TYPE")] = "1";
+        sbio->params[ctx->id("PIN_TYPE")] = 1;
         auto pu_attr = nxio->attrs.find(ctx->id("PULLUP"));
         if (pu_attr != nxio->attrs.end())
             sbio->params[ctx->id("PULLUP")] = pu_attr->second;
         replace_port(nxio, ctx->id("O"), sbio, ctx->id("D_IN_0"));
     } else if (nxio->type == ctx->id("$nextpnr_obuf")) {
-        sbio->params[ctx->id("PIN_TYPE")] = "25";
+        sbio->params[ctx->id("PIN_TYPE")] = 25;
         replace_port(nxio, ctx->id("I"), sbio, ctx->id("D_OUT_0"));
     } else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
         // N.B. tristate will be dealt with below
-        sbio->params[ctx->id("PIN_TYPE")] = "25";
+        sbio->params[ctx->id("PIN_TYPE")] = 25;
         replace_port(nxio, ctx->id("I"), sbio, ctx->id("D_OUT_0"));
         replace_port(nxio, ctx->id("O"), sbio, ctx->id("D_IN_0"));
     } else {
@@ -431,7 +431,7 @@ void nxio_to_sb(Context *ctx, CellInfo *nxio, CellInfo *sbio, std::unordered_set
             ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
             ctx->id("Y"));
     if (tbuf) {
-        sbio->params[ctx->id("PIN_TYPE")] = "41";
+        sbio->params[ctx->id("PIN_TYPE")] = 41;
         replace_port(tbuf, ctx->id("A"), sbio, ctx->id("D_OUT_0"));
         replace_port(tbuf, ctx->id("E"), sbio, ctx->id("OUTPUT_ENABLE"));
 
diff --git a/ice40/cells.h b/ice40/cells.h
index 3d9358da..777ca3e2 100644
--- a/ice40/cells.h
+++ b/ice40/cells.h
@@ -101,17 +101,19 @@ inline bool is_sb_pll40_pad(const BaseCtx *ctx, const CellInfo *cell)
     return cell->type == ctx->id("SB_PLL40_PAD") || cell->type == ctx->id("SB_PLL40_2_PAD") ||
            cell->type == ctx->id("SB_PLL40_2F_PAD") ||
            (cell->type == ctx->id("ICESTORM_PLL") &&
-            (cell->attrs.at(ctx->id("TYPE")) == "SB_PLL40_PAD" || cell->attrs.at(ctx->id("TYPE")) == "SB_PLL40_2_PAD" ||
-             cell->attrs.at(ctx->id("TYPE")) == "SB_PLL40_2F_PAD"));
+            (cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_PAD" ||
+             cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_2_PAD" ||
+             cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_2F_PAD"));
 }
 
 inline bool is_sb_pll40_dual(const BaseCtx *ctx, const CellInfo *cell)
 {
     return cell->type == ctx->id("SB_PLL40_2_PAD") || cell->type == ctx->id("SB_PLL40_2F_PAD") ||
            cell->type == ctx->id("SB_PLL40_2F_CORE") ||
-           (cell->type == ctx->id("ICESTORM_PLL") && (cell->attrs.at(ctx->id("TYPE")) == "SB_PLL40_2_PAD" ||
-                                                      cell->attrs.at(ctx->id("TYPE")) == "SB_PLL40_2F_PAD" ||
-                                                      cell->attrs.at(ctx->id("TYPE")) == "SB_PLL40_2F_CORE"));
+           (cell->type == ctx->id("ICESTORM_PLL") &&
+            (cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_2_PAD" ||
+             cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_2F_PAD" ||
+             cell->attrs.at(ctx->id("TYPE")).as_string() == "SB_PLL40_2F_CORE"));
 }
 
 uint8_t sb_pll40_type(const BaseCtx *ctx, const CellInfo *cell);
diff --git a/ice40/chains.cc b/ice40/chains.cc
index b3b54d6b..1b556f65 100644
--- a/ice40/chains.cc
+++ b/ice40/chains.cc
@@ -91,8 +91,8 @@ class ChainConstrainer
     {
         NPNR_ASSERT(cout_port.net != nullptr);
         std::unique_ptr<CellInfo> lc = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));
-        lc->params[ctx->id("LUT_INIT")] = "65280"; // 0xff00: O = I3
-        lc->params[ctx->id("CARRY_ENABLE")] = "1";
+        lc->params[ctx->id("LUT_INIT")] = Property(65280, 16); // 0xff00: O = I3
+        lc->params[ctx->id("CARRY_ENABLE")] = Property::State::S1;
         lc->ports.at(id_O).net = cout_port.net;
         std::unique_ptr<NetInfo> co_i3_net(new NetInfo());
         co_i3_net->name = ctx->id(lc->name.str(ctx) + "$I3");
@@ -167,9 +167,9 @@ class ChainConstrainer
     {
         NPNR_ASSERT(cin_port.net != nullptr);
         std::unique_ptr<CellInfo> lc = create_ice_cell(ctx, ctx->id("ICESTORM_LC"));
-        lc->params[ctx->id("CARRY_ENABLE")] = "1";
-        lc->params[ctx->id("CIN_CONST")] = "1";
-        lc->params[ctx->id("CIN_SET")] = "1";
+        lc->params[ctx->id("CARRY_ENABLE")] = Property::State::S1;
+        lc->params[ctx->id("CIN_CONST")] = Property::State::S1;
+        lc->params[ctx->id("CIN_SET")] = Property::State::S1;
         lc->ports.at(ctx->id("I1")).net = cin_port.net;
         cin_port.net->users.erase(std::remove_if(cin_port.net->users.begin(), cin_port.net->users.end(),
                                                  [cin_cell, cin_port](const PortRef &usr) {
diff --git a/ice40/main.cc b/ice40/main.cc
index 83cb04b0..b656f932 100644
--- a/ice40/main.cc
+++ b/ice40/main.cc
@@ -159,12 +159,12 @@ std::unique_ptr<Context> Ice40CommandHandler::createContext(std::unordered_map<s
         chipArgs.package = vm["package"].as<std::string>();
 
     if (values.find("arch.name") != values.end()) {
-        std::string arch_name = values["arch.name"].str;
+        std::string arch_name = values["arch.name"].as_string();
         if (arch_name != "ice40")
             log_error("Unsuported architecture '%s'.\n", arch_name.c_str());
     }
     if (values.find("arch.type") != values.end()) {
-        std::string arch_type = values["arch.type"].str;
+        std::string arch_type = values["arch.type"].as_string();
         if (chipArgs.type != ArchArgs::NONE)
             log_error("Overriding architecture is unsuported.\n");
 
@@ -195,7 +195,7 @@ std::unique_ptr<Context> Ice40CommandHandler::createContext(std::unordered_map<s
     if (values.find("arch.package") != values.end()) {
         if (vm.count("package"))
             log_error("Overriding architecture is unsuported.\n");
-        chipArgs.package = values["arch.package"].str;
+        chipArgs.package = values["arch.package"].as_string();
     }
 
     if (chipArgs.type == ArchArgs::NONE) {
@@ -214,13 +214,13 @@ std::unique_ptr<Context> Ice40CommandHandler::createContext(std::unordered_map<s
 
     ctx->settings[ctx->id("arch.package")] = ctx->archArgs().package;
     if (vm.count("promote-logic"))
-        ctx->settings[ctx->id("promote_logic")] = "1";
+        ctx->settings[ctx->id("promote_logic")] = Property::State::S1;
     if (vm.count("no-promote-globals"))
-        ctx->settings[ctx->id("no_promote_globals")] = "1";
+        ctx->settings[ctx->id("no_promote_globals")] = Property::State::S1;
     if (vm.count("opt-timing"))
-        ctx->settings[ctx->id("opt_timing")] = "1";
+        ctx->settings[ctx->id("opt_timing")] = Property::State::S1;
     if (vm.count("pcf-allow-unconstrained"))
-        ctx->settings[ctx->id("pcf_allow_unconstrained")] = "1";
+        ctx->settings[ctx->id("pcf_allow_unconstrained")] = Property::State::S1;
     return ctx;
 }
 
diff --git a/ice40/pack.cc b/ice40/pack.cc
index d1366c9c..462310cd 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -210,7 +210,7 @@ static void pack_carries(Context *ctx)
                 }
                 new_cells.push_back(std::move(created_lc));
             }
-            carry_lc->params[ctx->id("CARRY_ENABLE")] = "1";
+            carry_lc->params[ctx->id("CARRY_ENABLE")] = Property::State::S1;
             replace_port(ci, ctx->id("CI"), carry_lc, ctx->id("CIN"));
             replace_port(ci, ctx->id("CO"), carry_lc, ctx->id("COUT"));
             if (i0_net) {
@@ -230,8 +230,9 @@ static void pack_carries(Context *ctx)
             if (carry_lc->ports.at(ctx->id("CIN")).net != nullptr) {
                 IdString cin_net = carry_lc->ports.at(ctx->id("CIN")).net->name;
                 if (cin_net == ctx->id("$PACKER_GND_NET") || cin_net == ctx->id("$PACKER_VCC_NET")) {
-                    carry_lc->params[ctx->id("CIN_CONST")] = "1";
-                    carry_lc->params[ctx->id("CIN_SET")] = cin_net == ctx->id("$PACKER_VCC_NET") ? "1" : "0";
+                    carry_lc->params[ctx->id("CIN_CONST")] = Property::State::S1;
+                    carry_lc->params[ctx->id("CIN_SET")] =
+                            cin_net == ctx->id("$PACKER_VCC_NET") ? Property::State::S1 : Property::State::S0;
                     carry_lc->ports.at(ctx->id("CIN")).net = nullptr;
                     auto &cin_users = ctx->nets.at(cin_net)->users;
                     cin_users.erase(
@@ -270,9 +271,9 @@ static void pack_ram(Context *ctx)
             for (auto param : ci->params)
                 packed->params[param.first] = param.second;
             packed->params[ctx->id("NEG_CLK_W")] =
-                    std::to_string(ci->type == ctx->id("SB_RAM40_4KNW") || ci->type == ctx->id("SB_RAM40_4KNRNW"));
+                    Property(ci->type == ctx->id("SB_RAM40_4KNW") || ci->type == ctx->id("SB_RAM40_4KNRNW"), 1);
             packed->params[ctx->id("NEG_CLK_R")] =
-                    std::to_string(ci->type == ctx->id("SB_RAM40_4KNR") || ci->type == ctx->id("SB_RAM40_4KNRNW"));
+                    Property(ci->type == ctx->id("SB_RAM40_4KNR") || ci->type == ctx->id("SB_RAM40_4KNRNW"), 1);
             packed->type = ctx->id("ICESTORM_RAM");
             for (auto port : ci->ports) {
                 PortInfo &pi = port.second;
@@ -334,7 +335,7 @@ static void pack_constants(Context *ctx)
     log_info("Packing constants..\n");
 
     std::unique_ptr<CellInfo> gnd_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_GND");
-    gnd_cell->params[ctx->id("LUT_INIT")] = "0";
+    gnd_cell->params[ctx->id("LUT_INIT")] = Property(0, 16);
     std::unique_ptr<NetInfo> gnd_net = std::unique_ptr<NetInfo>(new NetInfo);
     gnd_net->name = ctx->id("$PACKER_GND_NET");
     gnd_net->driver.cell = gnd_cell.get();
@@ -347,7 +348,7 @@ static void pack_constants(Context *ctx)
     }
 
     std::unique_ptr<CellInfo> vcc_cell = create_ice_cell(ctx, ctx->id("ICESTORM_LC"), "$PACKER_VCC");
-    vcc_cell->params[ctx->id("LUT_INIT")] = "1";
+    vcc_cell->params[ctx->id("LUT_INIT")] = Property(1, 16);
     std::unique_ptr<NetInfo> vcc_net = std::unique_ptr<NetInfo>(new NetInfo);
     vcc_net->name = ctx->id("$PACKER_VCC_NET");
     vcc_net->driver.cell = vcc_cell.get();
@@ -417,13 +418,13 @@ static std::unique_ptr<CellInfo> create_padin_gbuf(Context *ctx, CellInfo *cell,
                                                    std::string gbuf_name)
 {
     // Find the matching SB_GB BEL connected to the same global network
-    BelId bel = ctx->getBelByName(ctx->id(cell->attrs[ctx->id("BEL")]));
+    BelId bel = ctx->getBelByName(ctx->id(cell->attrs[ctx->id("BEL")].as_string()));
     BelId gb_bel = find_padin_gbuf(ctx, bel, port_name);
     NPNR_ASSERT(gb_bel != BelId());
 
     // Create a SB_GB Cell and lock it there
     std::unique_ptr<CellInfo> gb = create_ice_cell(ctx, ctx->id("SB_GB"), gbuf_name);
-    gb->attrs[ctx->id("FOR_PAD_IN")] = "1";
+    gb->attrs[ctx->id("FOR_PAD_IN")] = Property::State::S1;
     gb->attrs[ctx->id("BEL")] = ctx->getBelName(gb_bel).str(ctx);
 
     // Reconnect the net to that port for easier identification it's a global net
@@ -521,7 +522,7 @@ static void pack_io(Context *ctx)
 
             // Make it a normal SB_IO with global marker
             ci->type = ctx->id("SB_IO");
-            ci->attrs[ctx->id("GLOBAL")] = "1";
+            ci->attrs[ctx->id("GLOBAL")] = Property::State::S1;
         } else if (is_sb_io(ctx, ci)) {
             // Disconnect unused inputs
             NetInfo *net_in0 = ci->ports.count(id_D_IN_0) ? ci->ports[id_D_IN_0].net : nullptr;
@@ -636,7 +637,7 @@ static void promote_globals(Context *ctx)
             /* And possibly limits what we can promote */
             if (cell.second->attrs.find(ctx->id("BEL")) != cell.second->attrs.end()) {
                 /* If the SB_GB is locked, doesn't matter what it drives */
-                BelId bel = ctx->getBelByName(ctx->id(cell.second->attrs[ctx->id("BEL")]));
+                BelId bel = ctx->getBelByName(ctx->id(cell.second->attrs[ctx->id("BEL")].as_string()));
                 int glb_id = ctx->getDrivenGlobalNetwork(bel);
                 if ((glb_id % 2) == 0)
                     resets_available--;
@@ -755,10 +756,10 @@ static void place_plls(Context *ctx)
 
         // If it's constrained already, add to already used list
         if (ci->attrs.count(ctx->id("BEL"))) {
-            BelId bel_constrain = ctx->getBelByName(ctx->id(ci->attrs[ctx->id("BEL")]));
+            BelId bel_constrain = ctx->getBelByName(ctx->id(ci->attrs[ctx->id("BEL")].as_string()));
             if (pll_all_bels.count(bel_constrain) == 0)
                 log_error("PLL '%s' is constrained to invalid BEL '%s'\n", ci->name.c_str(ctx),
-                          ci->attrs[ctx->id("BEL")].c_str());
+                          ci->attrs[ctx->id("BEL")].as_string().c_str());
             pll_used_bels[bel_constrain] = ci;
         }
 
@@ -790,7 +791,7 @@ static void place_plls(Context *ctx)
             log_error("PLL '%s' PACKAGEPIN SB_IO '%s' is unconstrained\n", ci->name.c_str(ctx),
                       io_cell->name.c_str(ctx));
 
-        BelId io_bel = ctx->getBelByName(ctx->id(io_cell->attrs.at(ctx->id("BEL"))));
+        BelId io_bel = ctx->getBelByName(ctx->id(io_cell->attrs.at(ctx->id("BEL")).as_string()));
         BelId found_bel;
 
         // Find the PLL BEL that would suit that connection
@@ -815,7 +816,7 @@ static void place_plls(Context *ctx)
         // Is it user constrained ?
         if (ci->attrs.count(ctx->id("BEL"))) {
             // Yes. Check it actually matches !
-            BelId bel_constrain = ctx->getBelByName(ctx->id(ci->attrs[ctx->id("BEL")]));
+            BelId bel_constrain = ctx->getBelByName(ctx->id(ci->attrs[ctx->id("BEL")].as_string()));
             if (bel_constrain != found_bel)
                 log_error("PLL '%s' is user constrained to %s but can only be placed in %s based on its PACKAGEPIN "
                           "connection\n",
@@ -845,7 +846,7 @@ static void place_plls(Context *ctx)
             continue;
 
         // Check all placed PLL (either forced by user, or forced by PACKAGEPIN)
-        BelId io_bel = ctx->getBelByName(ctx->id(io_ci->attrs[ctx->id("BEL")]));
+        BelId io_bel = ctx->getBelByName(ctx->id(io_ci->attrs[ctx->id("BEL")].as_string()));
 
         for (auto placed_pll : pll_used_bels) {
             BelPin pll_io_a, pll_io_b;
@@ -879,7 +880,7 @@ static void place_plls(Context *ctx)
             continue;
 
         // Check all placed PLL (either forced by user, or forced by PACKAGEPIN)
-        BelId gb_bel = ctx->getBelByName(ctx->id(gb_ci->attrs[ctx->id("BEL")]));
+        BelId gb_bel = ctx->getBelByName(ctx->id(gb_ci->attrs[ctx->id("BEL")].as_string()));
 
         for (auto placed_pll : pll_used_bels) {
             CellInfo *ci = placed_pll.second;
@@ -938,7 +939,7 @@ static void place_plls(Context *ctx)
             bool could_be_pad = false;
             BelId pad_bel;
             if (ni->users.size() == 1 && is_sb_io(ctx, ni->driver.cell) && ni->driver.cell->attrs.count(ctx->id("BEL")))
-                pad_bel = ctx->getBelByName(ctx->id(ni->driver.cell->attrs[ctx->id("BEL")]));
+                pad_bel = ctx->getBelByName(ctx->id(ni->driver.cell->attrs[ctx->id("BEL")].as_string()));
 
             // Find a BEL for it
             BelId found_bel;
@@ -989,7 +990,7 @@ static std::unique_ptr<CellInfo> spliceLUT(Context *ctx, CellInfo *ci, IdString
     // Create pass-through LUT.
     std::unique_ptr<CellInfo> pt = create_ice_cell(ctx, ctx->id("ICESTORM_LC"),
                                                    ci->name.str(ctx) + "$nextpnr_" + portId.str(ctx) + "_lut_through");
-    pt->params[ctx->id("LUT_INIT")] = "65280"; // output is always I3
+    pt->params[ctx->id("LUT_INIT")] = Property(65280, 16); // output is always I3
 
     // Create LUT output net.
     std::unique_ptr<NetInfo> out_net = std::unique_ptr<NetInfo>(new NetInfo);
@@ -1187,10 +1188,11 @@ static void pack_special(Context *ctx)
                     {std::make_tuple(id_SB_SPI, "0b0010"), Loc(25, 0, 1)},
                     {std::make_tuple(id_SB_I2C, "0b0011"), Loc(25, 31, 0)},
             };
-            if (map_ba74.find(std::make_tuple(ci->type, ci->params[ctx->id("BUS_ADDR74")])) == map_ba74.end())
+            if (map_ba74.find(std::make_tuple(ci->type, ci->params[ctx->id("BUS_ADDR74")].as_string())) ==
+                map_ba74.end())
                 log_error("Invalid value for BUS_ADDR74 for cell '%s' of type '%s'\n", ci->name.c_str(ctx),
                           ci->type.c_str(ctx));
-            Loc bel_loc = map_ba74.at(std::make_tuple(ci->type, ci->params[ctx->id("BUS_ADDR74")]));
+            Loc bel_loc = map_ba74.at(std::make_tuple(ci->type, ci->params[ctx->id("BUS_ADDR74")].as_string()));
             BelId bel = ctx->getBelByLocation(bel_loc);
             if (bel == BelId() || ctx->getBelType(bel) != ci->type)
                 log_error("Unable to find placement for cell '%s' of type '%s'\n", ci->name.c_str(ctx),
@@ -1230,12 +1232,12 @@ static void pack_special(Context *ctx)
             };
             for (auto param : ci->params)
                 if (pos_map_name.find(param.first) != pos_map_name.end()) {
-                    if (pos_map_val.find(param.second) == pos_map_val.end())
-                        log_error("Invalid PLL output selection '%s'\n", param.second.c_str());
-                    packed->params[pos_map_name.at(param.first)] = std::to_string(pos_map_val.at(param.second));
+                    if (pos_map_val.find(param.second.as_string()) == pos_map_val.end())
+                        log_error("Invalid PLL output selection '%s'\n", param.second.as_string().c_str());
+                    packed->params[pos_map_name.at(param.first)] = pos_map_val.at(param.second.as_string());
                 }
 
-            auto feedback_path = packed->params[ctx->id("FEEDBACK_PATH")];
+            auto feedback_path = packed->params[ctx->id("FEEDBACK_PATH")].as_string();
             std::string fbp_value =
                     feedback_path == "DELAY"
                             ? "0"
@@ -1247,8 +1249,8 @@ static void pack_special(Context *ctx)
             if (!std::all_of(fbp_value.begin(), fbp_value.end(), isdigit))
                 log_error("PLL '%s' has unsupported FEEDBACK_PATH value '%s'\n", ci->name.c_str(ctx),
                           feedback_path.c_str());
-            packed->params[ctx->id("FEEDBACK_PATH")] = fbp_value;
-            packed->params[ctx->id("PLLTYPE")] = std::to_string(sb_pll40_type(ctx, ci));
+            packed->params[ctx->id("FEEDBACK_PATH")] = Property(std::stoi(fbp_value), 3);
+            packed->params[ctx->id("PLLTYPE")] = sb_pll40_type(ctx, ci);
 
             NetInfo *pad_packagepin_net = nullptr;
 
@@ -1304,7 +1306,7 @@ static void pack_special(Context *ctx)
             }
 
             // PLL must have been placed already in place_plls()
-            BelId pll_bel = ctx->getBelByName(ctx->id(packed->attrs[ctx->id("BEL")]));
+            BelId pll_bel = ctx->getBelByName(ctx->id(packed->attrs[ctx->id("BEL")].as_string()));
             NPNR_ASSERT(pll_bel != BelId());
 
             // Deal with PAD PLL peculiarities
@@ -1448,7 +1450,7 @@ bool Arch::pack()
         ctx->assignArchInfo();
         constrain_chains(ctx);
         ctx->assignArchInfo();
-        ctx->settings[ctx->id("pack")] = "1";
+        ctx->settings[ctx->id("pack")] = 1;
         archInfoToAttributes();
         log_info("Checksum: 0x%08x\n", ctx->checksum());
         return true;
diff --git a/ice40/pcf.cc b/ice40/pcf.cc
index a854a780..8c61eb23 100644
--- a/ice40/pcf.cc
+++ b/ice40/pcf.cc
@@ -51,15 +51,15 @@ bool apply_pcf(Context *ctx, std::string filename, std::istream &in)
             bool nowarn = false;
             if (cmd == "set_io") {
                 size_t args_end = 1;
-                std::vector<std::pair<IdString, std::string>> extra_attrs;
+                std::vector<std::pair<IdString, Property>> extra_attrs;
                 while (args_end < words.size() && words.at(args_end).at(0) == '-') {
                     const auto &setting = words.at(args_end);
                     if (setting == "-pullup") {
                         const auto &value = words.at(++args_end);
                         if (value == "yes" || value == "1")
-                            extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP"), "1"));
+                            extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP"), Property::State::S1));
                         else if (value == "no" || value == "0")
-                            extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP"), "0"));
+                            extra_attrs.emplace_back(std::make_pair(ctx->id("PULLUP"), Property::State::S0));
                         else
                             log_error("Invalid value '%s' for -pullup (on line %d)\n", value.c_str(), lineno);
                     } else if (setting == "-pullup_resistor") {
@@ -96,7 +96,7 @@ bool apply_pcf(Context *ctx, std::string filename, std::istream &in)
                         log_error("duplicate pin constraint on '%s' (on line %d)\n", cell.c_str(), lineno);
                     fnd_cell->second->attrs[ctx->id("BEL")] = ctx->getBelName(pin_bel).str(ctx);
                     log_info("constrained '%s' to bel '%s'\n", cell.c_str(),
-                             fnd_cell->second->attrs[ctx->id("BEL")].c_str());
+                             fnd_cell->second->attrs[ctx->id("BEL")].as_string().c_str());
                     for (const auto &attr : extra_attrs)
                         fnd_cell->second->attrs[attr.first] = attr.second;
                 }