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authorSergiusz Bazanski <q3k@q3k.org>2018-07-12 20:24:00 +0100
committerSergiusz Bazanski <q3k@q3k.org>2018-07-12 20:24:00 +0100
commit681d82413191e5379bd5d0147d05a0879e005c49 (patch)
tree8c695352188dfa696ec9878816f06866f060ede2 /ice40/chipdb.py
parent284b4750ee6a3a5a4e33590cbbccaaccfd2c5899 (diff)
parentf9ef4cd4bdeaccef6fd1522441be8fd0f80249c1 (diff)
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Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/fix-zoom
Diffstat (limited to 'ice40/chipdb.py')
-rw-r--r--ice40/chipdb.py35
1 files changed, 34 insertions, 1 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 2a918ed9..00194deb 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -11,6 +11,7 @@ group.add_argument("-b", "--binary", action="store_true")
group.add_argument("-c", "--c_file", action="store_true")
parser.add_argument("filename", type=str, help="chipdb input filename")
parser.add_argument("-p", "--portspins", type=str, help="path to portpins.inc")
+parser.add_argument("-g", "--gfxh", type=str, help="path to gfx.h")
args = parser.parse_args()
endianness = "le"
@@ -54,6 +55,9 @@ beltypes = dict()
tiletypes = dict()
wiretypes = dict()
+gfx_wire_ids = dict()
+wire_segments = dict()
+
with open(args.portspins) as f:
for line in f:
line = line.replace("(", " ")
@@ -66,6 +70,18 @@ with open(args.portspins) as f:
idx = len(portpins) + 1
portpins[line[1]] = idx
+with open(args.gfxh) as f:
+ state = 0
+ for line in f:
+ if state == 0 and line.startswith("enum GfxTileWireId "):
+ state = 1
+ elif state == 1 and line.startswith("};"):
+ state = 0
+ elif state == 1:
+ idx = len(gfx_wire_ids)
+ name = line.strip().rstrip(",")
+ gfx_wire_ids[name] = idx
+
beltypes["ICESTORM_LC"] = 1
beltypes["ICESTORM_RAM"] = 2
beltypes["SB_IO"] = 3
@@ -371,6 +387,10 @@ with open(args.filename, "r") as f:
if mode[1] not in wire_xy:
wire_xy[mode[1]] = list()
wire_xy[mode[1]].append((int(line[0]), int(line[1])))
+ if mode[1] not in wire_segments:
+ wire_segments[mode[1]] = set()
+ if ("TILE_WIRE_" + wname[2].upper()) in gfx_wire_ids:
+ wire_segments[mode[1]].add((wname[0], wname[1], gfx_wire_ids["TILE_WIRE_" + wname[2].upper()]))
continue
if mode[0] in ("buffer", "routing"):
@@ -1040,7 +1060,7 @@ for t in range(num_tile_types):
tileinfo.append(ti)
bba.l("wire_data_%s" % dev_name, "WireInfoPOD")
-for info in wireinfo:
+for wire, info in enumerate(wireinfo):
bba.s(info["name"], "name")
bba.u32(info["num_uphill"], "num_uphill")
bba.u32(info["num_downhill"], "num_downhill")
@@ -1050,11 +1070,24 @@ for info in wireinfo:
bba.u32(info["uphill_bel"], "bel_uphill.bel_index")
bba.u32(info["uphill_pin"], "bel_uphill.port")
bba.r(info["list_bels_downhill"], "bels_downhill")
+ bba.u32(len(wire_segments[wire]), "num_segments")
+ if len(wire_segments[wire]):
+ bba.r("wire_segments_%d" % wire, "segments")
+ else:
+ bba.u32(0, "segments")
bba.u8(info["x"], "x")
bba.u8(info["y"], "y")
bba.u8(wiretypes[wire_type(info["name"])], "type")
bba.u8(0, "padding")
+for wire in range(num_wires):
+ if len(wire_segments[wire]):
+ bba.l("wire_segments_%d" % wire, "WireSegmentPOD")
+ for seg in sorted(wire_segments[wire]):
+ bba.u8(seg[0], "x")
+ bba.u8(seg[1], "y")
+ bba.u16(seg[2], "index")
+
bba.l("pip_data_%s" % dev_name, "PipInfoPOD")
for info in pipinfo:
bba.u32(info["src"], "src")