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authorDavid Shah <dave@ds0.me>2020-07-02 13:32:30 +0100
committerGitHub <noreply@github.com>2020-07-02 13:32:30 +0100
commit137241cfef385a68d2ce732a5b3283458790543d (patch)
treebff5c42b4c43f89281a6ce967411785a17db3d25 /ice40/chipdb.py
parent4a2964c91568c63928f1d916aef1a1b84a9e608d (diff)
parent72786e249a2c099b3434a270840d007f7178105c (diff)
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Merge pull request #463 from YosysHQ/fix-archcheck
Fix arch checks, and add these to CI
Diffstat (limited to 'ice40/chipdb.py')
-rw-r--r--ice40/chipdb.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 7b3ad999..efdde1a1 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -1060,7 +1060,7 @@ for tile_xy, tile_type in sorted(tiles.items()):
if ec[1] == tile_xy[0] and ec[2] == tile_xy[1]:
add_bel_ec(ec)
-for ec in sorted(extra_cells.keys()):
+for ec in sorted(extra_cells.keys(), key=lambda ec: (ec[1], ec[2], ec[3], ec[0])):
if ec[1] in (0, dev_width - 1) and ec[2] in (0, dev_height - 1):
add_bel_ec(ec)