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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2018-08-03 23:44:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2018-08-03 23:44:55 -0700 |
| commit | 0a14e20f7332344d4c2f73c7ede54ef0258997f7 (patch) | |
| tree | 37250740746ae2a6f19fff60891ba42846569f85 /ice40/chipdb.py | |
| parent | 45304d049f1c939ca3ac9782a1108f17e784a1cd (diff) | |
| parent | 65d73eb9838e0bb8e6d089ecde3d4ffaf34e9e29 (diff) | |
| download | nextpnr-0a14e20f7332344d4c2f73c7ede54ef0258997f7.tar.gz nextpnr-0a14e20f7332344d4c2f73c7ede54ef0258997f7.tar.bz2 nextpnr-0a14e20f7332344d4c2f73c7ede54ef0258997f7.zip | |
Merge branch 'master' into slack_histogram
Conflicts:
common/placer1.cc
Diffstat (limited to 'ice40/chipdb.py')
| -rw-r--r-- | ice40/chipdb.py | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/ice40/chipdb.py b/ice40/chipdb.py index a0d7f03c..d782013f 100644 --- a/ice40/chipdb.py +++ b/ice40/chipdb.py @@ -716,7 +716,9 @@ tmport_to_portpin = { "WCLKE": "WCLKE", "WE": "WE", "posedge:CLOCK": "CLOCK", - "posedge:SLEEP": "SLEEP" + "posedge:SLEEP": "SLEEP", + "USERSIGNALTOGLOBALBUFFER": "USER_SIGNAL_TO_GLOBAL_BUFFER", + "GLOBALBUFFEROUTPUT": "GLOBAL_BUFFER_OUTPUT" } for i in range(16): @@ -744,6 +746,8 @@ def add_cell_timingdata(bel_type, timing_cell, fast_db, slow_db): cell_timings[bel_type] = timing_entries add_cell_timingdata("ICESTORM_LC", "LogicCell40", fast_timings, slow_timings) +add_cell_timingdata("SB_GB", "ICE_GB", fast_timings, slow_timings) + if dev_name != "384": add_cell_timingdata("ICESTORM_RAM", "SB_RAM40_4K", fast_timings, slow_timings) if dev_name == "5k": |