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| author | Sylvain Munaut <tnt@246tNt.com> | 2019-03-22 23:29:34 +0100 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2019-03-25 23:48:59 +0100 |
| commit | d401e3e1a09e2e5d78f18f32405c82293ce68545 (patch) | |
| tree | fe46510d61a491a9d1b85ffba102e0eb9c69b8c2 /ice40/cells.cc | |
| parent | c2d87846d8e6c9603f432c1b021f58023f7625b4 (diff) | |
| download | nextpnr-d401e3e1a09e2e5d78f18f32405c82293ce68545.tar.gz nextpnr-d401e3e1a09e2e5d78f18f32405c82293ce68545.tar.bz2 nextpnr-d401e3e1a09e2e5d78f18f32405c82293ce68545.zip | |
ice40: Add support for SB_I2C and SB_SPI
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Diffstat (limited to 'ice40/cells.cc')
| -rw-r--r-- | ice40/cells.cc | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/ice40/cells.cc b/ice40/cells.cc index 35a5346f..5744fe50 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -275,6 +275,53 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri add_port(ctx, new_cell.get(), "PWMOUT1", PORT_OUT); add_port(ctx, new_cell.get(), "PWMOUT2", PORT_OUT); add_port(ctx, new_cell.get(), "LEDDON", PORT_OUT); + } else if (type == ctx->id("SB_I2C")) { + new_cell->params[ctx->id("I2C_SLAVE_INIT_ADDR")] = "0b1111100001"; + new_cell->params[ctx->id("BUS_ADDR74")] = "0b0001"; + for (int i = 0; i < 8; i++) { + add_port(ctx, new_cell.get(), "SBADRI" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "SBDATI" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "SBDATO" + std::to_string(i), PORT_OUT); + } + add_port(ctx, new_cell.get(), "SBCLKI", PORT_IN); + add_port(ctx, new_cell.get(), "SBRWI", PORT_IN); + add_port(ctx, new_cell.get(), "SBSTBI", PORT_IN); + add_port(ctx, new_cell.get(), "SCLI", PORT_IN); + add_port(ctx, new_cell.get(), "SDAI", PORT_IN); + add_port(ctx, new_cell.get(), "SBACKO", PORT_OUT); + add_port(ctx, new_cell.get(), "I2CIRQ", PORT_OUT); + add_port(ctx, new_cell.get(), "I2CWKUP", PORT_OUT); + add_port(ctx, new_cell.get(), "SCLO", PORT_OUT); + add_port(ctx, new_cell.get(), "SCLOE", PORT_OUT); + add_port(ctx, new_cell.get(), "SDAO", PORT_OUT); + add_port(ctx, new_cell.get(), "SDAOE", PORT_OUT); + } else if (type == ctx->id("SB_SPI")) { + new_cell->params[ctx->id("BUS_ADDR74")] = "0b0000"; + for (int i = 0; i < 8; i++) { + add_port(ctx, new_cell.get(), "SBADRI" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "SBDATI" + std::to_string(i), PORT_IN); + add_port(ctx, new_cell.get(), "SBDATO" + std::to_string(i), PORT_OUT); + } + add_port(ctx, new_cell.get(), "SBCLKI", PORT_IN); + add_port(ctx, new_cell.get(), "SBRWI", PORT_IN); + add_port(ctx, new_cell.get(), "SBSTBI", PORT_IN); + add_port(ctx, new_cell.get(), "MI", PORT_IN); + add_port(ctx, new_cell.get(), "SI", PORT_IN); + add_port(ctx, new_cell.get(), "SCKI", PORT_IN); + add_port(ctx, new_cell.get(), "SCSNI", PORT_IN); + add_port(ctx, new_cell.get(), "SBACKO", PORT_OUT); + add_port(ctx, new_cell.get(), "SPIIRQ", PORT_OUT); + add_port(ctx, new_cell.get(), "SPIWKUP", PORT_OUT); + add_port(ctx, new_cell.get(), "SO", PORT_OUT); + add_port(ctx, new_cell.get(), "SOE", PORT_OUT); + add_port(ctx, new_cell.get(), "MO", PORT_OUT); + add_port(ctx, new_cell.get(), "MOE", PORT_OUT); + add_port(ctx, new_cell.get(), "SCKO", PORT_OUT); + add_port(ctx, new_cell.get(), "SCKOE", PORT_OUT); + for (int i = 0; i < 4; i++) { + add_port(ctx, new_cell.get(), "MCSNO" + std::to_string(i), PORT_OUT); + add_port(ctx, new_cell.get(), "MCSNOE" + std::to_string(i), PORT_OUT); + } } else { log_error("unable to create iCE40 cell of type %s", type.c_str(ctx)); } |