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authorSergiusz Bazanski <q3k@q3k.org>2018-08-19 13:02:24 +0100
committerSergiusz Bazanski <q3k@q3k.org>2018-08-19 21:30:55 +0100
commit1bf22a7f64b8ac7f8d7677f4c65b9fef275910dd (patch)
tree9d1e388af654909a9a574c8d5333a7a3276847ed /ice40/cells.cc
parent26be6f9761bba9dff646c6b1d071b149bd26f950 (diff)
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ice40: make PLL packing more robust
Diffstat (limited to 'ice40/cells.cc')
-rw-r--r--ice40/cells.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/ice40/cells.cc b/ice40/cells.cc
index 5bdc7990..e79a1fda 100644
--- a/ice40/cells.cc
+++ b/ice40/cells.cc
@@ -28,6 +28,7 @@ NEXTPNR_NAMESPACE_BEGIN
void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
{
IdString id = ctx->id(name);
+ NPNR_ASSERT(cell->ports.count(id) == 0);
cell->ports[id] = PortInfo{id, nullptr, dir};
}
@@ -237,7 +238,7 @@ std::unique_ptr<CellInfo> create_ice_cell(Context *ctx, IdString type, std::stri
add_port(ctx, new_cell.get(), "SCLK", PORT_IN);
add_port(ctx, new_cell.get(), "SDI", PORT_IN);
- add_port(ctx, new_cell.get(), "SDI", PORT_OUT);
+ add_port(ctx, new_cell.get(), "SDO", PORT_OUT);
add_port(ctx, new_cell.get(), "LOCK", PORT_OUT);
add_port(ctx, new_cell.get(), "PLLOUT_A", PORT_OUT);