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| author | Clifford Wolf <clifford@clifford.at> | 2018-06-20 12:50:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-06-20 12:50:38 +0200 |
| commit | c3837027b22b67a5079d84419bae20c4d545430b (patch) | |
| tree | 49196c574fdda739506d7c78df6a96960620590f /ice40/arch.h | |
| parent | a06d2aeb4da0c51fb50d8283367836e6dbf91b4d (diff) | |
| download | nextpnr-c3837027b22b67a5079d84419bae20c4d545430b.tar.gz nextpnr-c3837027b22b67a5079d84419bae20c4d545430b.tar.bz2 nextpnr-c3837027b22b67a5079d84419bae20c4d545430b.zip | |
Add better iCE40 delay estimates
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'ice40/arch.h')
| -rw-r--r-- | ice40/arch.h | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/ice40/arch.h b/ice40/arch.h index c1256a41..4a2f6e50 100644 --- a/ice40/arch.h +++ b/ice40/arch.h @@ -63,6 +63,17 @@ enum PortPin : int32_t PIN_MAXIDX }; +enum WireType : int8_t +{ + WIRE_TYPE_NONE = 0, + WIRE_TYPE_LOCAL = 1, + WIRE_TYPE_GLOBAL = 2, + WIRE_TYPE_SP4_VERT = 3, + WIRE_TYPE_SP4_HORZ = 4, + WIRE_TYPE_SP12_HORZ = 5, + WIRE_TYPE_SP12_VERT = 6 +}; + // ----------------------------------------------------------------------- /**** Everything in this section must be kept in sync with chipdb.py ****/ @@ -130,7 +141,9 @@ struct WireInfoPOD BelPortPOD bel_uphill; RelPtr<BelPortPOD> bels_downhill; - int16_t x, y; + int8_t x, y; + WireType type; + int8_t padding_0; } __attribute__((packed)); struct PackagePinPOD @@ -742,6 +755,8 @@ struct Arch : BaseCtx bool estimatePosition(BelId bel, int &x, int &y) const; delay_t estimateDelay(WireId src, WireId dst) const; + delay_t getDelayEpsilon() const { return 10; } + float getDelayNS(delay_t v) const { return v * 0.001; } // ------------------------------------------------- |