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author | David Shah <dave@ds0.me> | 2021-01-28 12:53:03 +0000 |
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committer | GitHub <noreply@github.com> | 2021-01-28 12:53:03 +0000 |
commit | b671d8f59d425b6faf07167b7360cecd12366151 (patch) | |
tree | 552ddbb947435eb5e3c44940a16d3733697766b2 /gui | |
parent | a95d6678b1d353a1606e377e1833dec54ad4ee65 (diff) | |
parent | b87ab0ee9de093b5302de7997e94e10dae6655b4 (diff) | |
download | nextpnr-b671d8f59d425b6faf07167b7360cecd12366151.tar.gz nextpnr-b671d8f59d425b6faf07167b7360cecd12366151.tar.bz2 nextpnr-b671d8f59d425b6faf07167b7360cecd12366151.zip |
Merge pull request #553 from YosysHQ/rel-slice
Switch from RelPtr to RelSlice
Diffstat (limited to 'gui')
-rw-r--r-- | gui/designwidget.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gui/designwidget.cc b/gui/designwidget.cc index 457b7de4..f856b5f6 100644 --- a/gui/designwidget.cc +++ b/gui/designwidget.cc @@ -306,7 +306,7 @@ void DesignWidget::newContext(Context *ctx) {
TreeModel::ElementXYRoot<WireId>::ElementMap wireMap;
#ifdef ARCH_ICE40
- for (int i = 0; i < ctx->chip_info->num_wires; i++) {
+ for (int i = 0; i < int(ctx->chip_info->wire_data.size()); i++) {
const auto wire = &ctx->chip_info->wire_data[i];
WireId wireid;
wireid.index = i;
|