lutram actually PnRs

5 files changed, 43 insertions, 38 deletions

diff --git a/gowin/arch.cc b/gowin/arch.cc
index d554bd64..cba492ab 100644
--- a/gowin/arch.cc
+++ b/gowin/arch.cc
@@ -791,39 +791,6 @@ void Arch::read_cst(std::istream &in)
     settings[id_cst] = 1;
 }
 
-void Arch::addShadowRamBels(const DatabasePOD *db, int row, int col)
-{
-    IdString belname, bel_id;
-    char buf[32];
-    snprintf(buf, 32, "R%dC%d_RAMW", row + 1, col + 1);
-    belname = id(buf);
-    addBel(belname, id_RAMW, Loc(col, row, BelZ::lutram_0_z), false);
-
-    snprintf(buf, 32, "R%dC%d_A%d", row + 1, col + 1, 4);
-    addBelInput(belname, id_A4, id(buf));
-    snprintf(buf, 32, "R%dC%d_B%d", row + 1, col + 1, 4);
-    addBelInput(belname, id_B4, id(buf));
-    snprintf(buf, 32, "R%dC%d_C%d", row + 1, col + 1, 4);
-    addBelInput(belname, id_C4, id(buf));
-    snprintf(buf, 32, "R%dC%d_D%d", row + 1, col + 1, 4);
-    addBelInput(belname, id_D4, id(buf));
-
-    snprintf(buf, 32, "R%dC%d_A%d", row + 1, col + 1, 5);
-    addBelInput(belname, id_A5, id(buf));
-    snprintf(buf, 32, "R%dC%d_B%d", row + 1, col + 1, 5);
-    addBelInput(belname, id_B5, id(buf));
-    snprintf(buf, 32, "R%dC%d_C%d", row + 1, col + 1, 5);
-    addBelInput(belname, id_C5, id(buf));
-    snprintf(buf, 32, "R%dC%d_D%d", row + 1, col + 1, 5);
-    addBelInput(belname, id_D5, id(buf));
-
-    snprintf(buf, 32, "R%dC%d_CLK%d", row + 1, col + 1, 2);
-    addBelInput(belname, id_CLK, id(buf));
-    snprintf(buf, 32, "R%dC%d_LSR%d", row + 1, col + 1, 2);
-    addBelInput(belname, id_LSR, id(buf));
-}
-
-
 // Add all MUXes for the cell
 void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
 {
@@ -1100,6 +1067,34 @@ Arch::Arch(ArchArgs args) : args(args)
                 snprintf(buf, 32, "R%dC%d_%s", row + 1, col + 1, portname.c_str(this));
                 addBelInput(belname, id_OSCEN, id(buf));
                 break;
+            case ID_RAM16:
+                snprintf(buf, 32, "R%dC%d_RAMW", row + 1, col + 1);
+                belname = id(buf);
+                addBel(belname, id_RAMW, Loc(col, row, BelZ::lutram_0_z), false);
+
+                snprintf(buf, 32, "R%dC%d_A%d", row + 1, col + 1, 4);
+                addBelInput(belname, id_A4, id(buf));
+                snprintf(buf, 32, "R%dC%d_B%d", row + 1, col + 1, 4);
+                addBelInput(belname, id_B4, id(buf));
+                snprintf(buf, 32, "R%dC%d_C%d", row + 1, col + 1, 4);
+                addBelInput(belname, id_C4, id(buf));
+                snprintf(buf, 32, "R%dC%d_D%d", row + 1, col + 1, 4);
+                addBelInput(belname, id_D4, id(buf));
+
+                snprintf(buf, 32, "R%dC%d_A%d", row + 1, col + 1, 5);
+                addBelInput(belname, id_A5, id(buf));
+                snprintf(buf, 32, "R%dC%d_B%d", row + 1, col + 1, 5);
+                addBelInput(belname, id_B5, id(buf));
+                snprintf(buf, 32, "R%dC%d_C%d", row + 1, col + 1, 5);
+                addBelInput(belname, id_C5, id(buf));
+                snprintf(buf, 32, "R%dC%d_D%d", row + 1, col + 1, 5);
+                addBelInput(belname, id_D5, id(buf));
+
+                snprintf(buf, 32, "R%dC%d_CLK%d", row + 1, col + 1, 2);
+                addBelInput(belname, id_CLK, id(buf));
+                snprintf(buf, 32, "R%dC%d_LSR%d", row + 1, col + 1, 2);
+                addBelInput(belname, id_LSR, id(buf));
+                break;
             // fall through the ++
             case ID_LUT7:
                 z++;
@@ -1145,9 +1140,6 @@ Arch::Arch(ArchArgs args) : args(args)
                 if (z == 0) {
                     addMuxBels(db, row, col);
                 }
-                if (z == 4) {
-                    addShadowRamBels(db, row, col);
-                }
                 if (z % 2 == 0) {
                     snprintf(buf, 32, "R%dC%d_LUT_GRP%d", row + 1, col + 1, z);
                     grpname = id(buf);
diff --git a/gowin/arch.h b/gowin/arch.h
index 80f887bb..c13cdf09 100644
--- a/gowin/arch.h
+++ b/gowin/arch.h
@@ -344,7 +344,6 @@ struct Arch : BaseArch<ArchRanges>
     DelayQuad getWireTypeDelay(IdString wire);
     void read_cst(std::istream &in);
     void addMuxBels(const DatabasePOD *db, int row, int col);
-    void addShadowRamBels(const DatabasePOD *db, int row, int col);
 
     // ---------------------------------------------------------------
     // Common Arch API. Every arch must provide the following methods.
diff --git a/gowin/cells.cc b/gowin/cells.cc
index 8285dc4e..63ee71ed 100644
--- a/gowin/cells.cc
+++ b/gowin/cells.cc
@@ -48,6 +48,13 @@ std::unique_ptr<CellInfo> create_generic_cell(Context *ctx, IdString type, std::
         new_cell->addOutput(id_Q);
         new_cell->addInput(id_CE);
         new_cell->addInput(id_LSR);
+    } else if (type == id_RAMW) {
+        IdString names[8] = {id_A4, id_B4, id_C4, id_D4, id_A5, id_B5, id_C5, id_D5};
+        for (int i = 0; i < 8; i++) {
+            new_cell->addInput(names[i]);
+        }
+        new_cell->addInput(id_CLK);
+        new_cell->addInput(id_LSR);
     } else if (type == id_GW_MUX2_LUT5 || type == id_GW_MUX2_LUT6 || type == id_GW_MUX2_LUT7 ||
                type == id_GW_MUX2_LUT7 || type == id_GW_MUX2_LUT8) {
         new_cell->addInput(id_I0);
@@ -190,6 +197,9 @@ void sram_to_slice(Context *ctx, CellInfo *ram, CellInfo *slice, int index)
     if (slice->hierpath == IdString())
         slice->hierpath = slice->hierpath;
 
+    snprintf(buf1, 32, "INIT_%d", index);
+    slice->params[id_INIT] = ram->params[ctx->id(buf1)];
+
     snprintf(buf1, 32, "DO[%d]", index);
     ram->movePortTo(ctx->id(buf1), slice, id_F);
 
diff --git a/gowin/constids.inc b/gowin/constids.inc
index d9ca1f0c..0c788ecd 100644
--- a/gowin/constids.inc
+++ b/gowin/constids.inc
@@ -749,6 +749,7 @@ X(DFFNC)
 X(DFFNCE)
 
 // Shadow RAM
+X(RAM16)
 X(RAMW)
 X(RAM16SDP4)
 X(WADA)
diff --git a/gowin/pack.cc b/gowin/pack.cc
index fa88772a..7d3a8e98 100644
--- a/gowin/pack.cc
+++ b/gowin/pack.cc
@@ -695,6 +695,8 @@ static void pack_gsr(Context *ctx)
 // Pack shadow RAM
 void pack_sram(Context *ctx)
 {
+    log_info("Packing Shadow RAM..\n");
+
     pool<IdString> packed_cells;
     std::vector<std::unique_ptr<CellInfo>> new_cells;
 
@@ -755,7 +757,7 @@ void pack_sram(Context *ctx)
             ramw_slice->constr_abs_z = true;
             ramw_slice->constr_x = 0;
             ramw_slice->constr_y = 0;
-            ramw_slice->constr_z = 4;
+            ramw_slice->constr_z = BelZ::lutram_0_z;
             ram_comb[0]->constr_children.push_back(ramw_slice.get());
 
             for (int i = 0; i < 4; i++)
@@ -1091,6 +1093,7 @@ bool Arch::pack()
     try {
         log_break();
         pack_constants(ctx);
+        pack_sram(ctx);
         pack_gsr(ctx);
         pack_io(ctx);
         pack_diff_io(ctx);