Merge branch 'master' into redist_slack

2 files changed, 49 insertions, 30 deletions

diff --git a/generic/arch.cc b/generic/arch.cc
index b9ec1695..f5e94778 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -62,28 +62,38 @@ void Arch::addAlias(IdString name, IdString srcWire, IdString dstWire, DelayInfo
     pip_ids.push_back(name);
 }
 
-void Arch::addBel(IdString name, IdString type, int x, int y, int z, bool gb)
+void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
 {
-    Loc loc;
-    loc.x = x;
-    loc.y = y;
-    loc.z = z;
-
     NPNR_ASSERT(bels.count(name) == 0);
     NPNR_ASSERT(bel_by_loc.count(loc) == 0);
     BelInfo &bi = bels[name];
     bi.name = name;
     bi.type = type;
-    bi.x = x;
-    bi.y = y;
-    bi.z = z;
+    bi.x = loc.x;
+    bi.y = loc.y;
+    bi.z = loc.z;
     bi.gb = gb;
 
     bel_ids.push_back(name);
-    bel_ids_by_type[type].push_back(name);
-
     bel_by_loc[loc] = name;
-    bels_by_tile[x][y].push_back(name);
+
+    if (bels_by_tile.size() <= loc.x)
+        bels_by_tile.resize(loc.x + 1);
+
+    if (bels_by_tile[loc.x].size() <= loc.y)
+        bels_by_tile[loc.x].resize(loc.y + 1);
+
+    bels_by_tile[loc.x][loc.y].push_back(name);
+
+    if (tileDimZ.size() <= loc.x)
+        tileDimZ.resize(loc.x + 1);
+
+    if (tileDimZ[loc.x].size() <= loc.y)
+        tileDimZ[loc.x].resize(loc.y + 1);
+
+    gridDimX = std::max(gridDimX, loc.x + 1);
+    gridDimY = std::max(gridDimY, loc.x + 1);
+    tileDimZ[loc.x][loc.y] = std::max(tileDimZ[loc.x][loc.y], loc.z + 1);
 }
 
 void Arch::addBelInput(IdString bel, IdString name, IdString wire)
@@ -95,6 +105,7 @@ void Arch::addBelInput(IdString bel, IdString name, IdString wire)
     pi.type = PORT_IN;
 
     wires.at(wire).downhill_bel_pins.push_back(BelPin{bel, name});
+    wires.at(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
 void Arch::addBelOutput(IdString bel, IdString name, IdString wire)
@@ -106,6 +117,7 @@ void Arch::addBelOutput(IdString bel, IdString name, IdString wire)
     pi.type = PORT_OUT;
 
     wires.at(wire).uphill_bel_pin = BelPin{bel, name};
+    wires.at(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
 void Arch::addBelInout(IdString bel, IdString name, IdString wire)
@@ -117,6 +129,7 @@ void Arch::addBelInout(IdString bel, IdString name, IdString wire)
     pi.type = PORT_INOUT;
 
     wires.at(wire).downhill_bel_pins.push_back(BelPin{bel, name});
+    wires.at(wire).bel_pins.push_back(BelPin{bel, name});
 }
 
 void Arch::addGroupBel(IdString group, IdString bel) { groups[group].bels.push_back(bel); }
@@ -210,21 +223,18 @@ IdString Arch::getConflictingBelCell(BelId bel) const { return bels.at(bel).boun
 
 const std::vector<BelId> &Arch::getBels() const { return bel_ids; }
 
-const std::vector<BelId> &Arch::getBelsByType(BelType type) const
-{
-    static std::vector<BelId> empty_list;
-    if (bel_ids_by_type.count(type))
-        return bel_ids_by_type.at(type);
-    return empty_list;
-}
-
 BelType Arch::getBelType(BelId bel) const { return bels.at(bel).type; }
 
-WireId Arch::getWireBelPin(BelId bel, PortPin pin) const { return bels.at(bel).pins.at(pin).wire; }
+WireId Arch::getBelPinWire(BelId bel, PortPin pin) const { return bels.at(bel).pins.at(pin).wire; }
 
-BelPin Arch::getBelPinUphill(WireId wire) const { return wires.at(wire).uphill_bel_pin; }
+PortType Arch::getBelPinType(BelId bel, PortPin pin) const { return bels.at(bel).pins.at(pin).type; }
 
-const std::vector<BelPin> &Arch::getBelPinsDownhill(WireId wire) const { return wires.at(wire).downhill_bel_pins; }
+std::vector<PortPin> Arch::getBelPins(BelId bel) const
+{
+    std::vector<PortPin> ret;
+    for (auto &it : bels.at(bel).pins)
+        ret.push_back(it.first);
+}
 
 // ---------------------------------------------------------------
 
@@ -272,6 +282,8 @@ IdString Arch::getBoundWireNet(WireId wire) const { return wires.at(wire).bound_
 
 IdString Arch::getConflictingWireNet(WireId wire) const { return wires.at(wire).bound_net; }
 
+const std::vector<BelPin> &Arch::getWireBelPins(WireId wire) const { return wires.at(wire).bel_pins; }
+
 const std::vector<WireId> &Arch::getWires() const { return wire_ids; }
 
 // ---------------------------------------------------------------
diff --git a/generic/arch.h b/generic/arch.h
index 977cc4d5..2b952da6 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -43,6 +43,7 @@ struct WireInfo
     std::vector<PipId> downhill, uphill, aliases;
     BelPin uphill_bel_pin;
     std::vector<BelPin> downhill_bel_pins;
+    std::vector<BelPin> bel_pins;
     DecalXY decalxy;
     int x, y;
 };
@@ -83,21 +84,23 @@ struct Arch : BaseCtx
     std::unordered_map<GroupId, GroupInfo> groups;
 
     std::vector<IdString> bel_ids, wire_ids, pip_ids;
-    std::unordered_map<IdString, std::vector<IdString>> bel_ids_by_type;
 
     std::unordered_map<Loc, BelId> bel_by_loc;
-    std::unordered_map<int, std::unordered_map<int, std::vector<BelId>>> bels_by_tile;
+    std::vector<std::vector<std::vector<BelId>>> bels_by_tile;
 
     std::unordered_map<DecalId, std::vector<GraphicElement>> decal_graphics;
     DecalXY frame_decalxy;
 
+    int gridDimX, gridDimY;
+    std::vector<std::vector<int>> tileDimZ;
+
     float grid_distance_to_delay;
 
     void addWire(IdString name, int x, int y);
     void addPip(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay);
     void addAlias(IdString name, IdString srcWire, IdString dstWire, DelayInfo delay);
 
-    void addBel(IdString name, IdString type, int x, int y, int z, bool gb);
+    void addBel(IdString name, IdString type, Loc loc, bool gb);
     void addBelInput(IdString bel, IdString name, IdString wire);
     void addBelOutput(IdString bel, IdString name, IdString wire);
     void addBelInout(IdString bel, IdString name, IdString wire);
@@ -130,6 +133,10 @@ struct Arch : BaseCtx
     BelType belTypeFromId(IdString id) const { return id; }
     PortPin portPinFromId(IdString id) const { return id; }
 
+    int getGridDimX() const { return gridDimX; }
+    int getGridDimY() const { return gridDimY; }
+    int getTileDimZ(int x, int y) const { return tileDimZ[x][y]; }
+
     BelId getBelByName(IdString name) const;
     IdString getBelName(BelId bel) const;
     Loc getBelLocation(BelId bel) const;
@@ -143,11 +150,10 @@ struct Arch : BaseCtx
     IdString getBoundBelCell(BelId bel) const;
     IdString getConflictingBelCell(BelId bel) const;
     const std::vector<BelId> &getBels() const;
-    const std::vector<BelId> &getBelsByType(BelType type) const;
     BelType getBelType(BelId bel) const;
-    WireId getWireBelPin(BelId bel, PortPin pin) const;
-    BelPin getBelPinUphill(WireId wire) const;
-    const std::vector<BelPin> &getBelPinsDownhill(WireId wire) const;
+    WireId getBelPinWire(BelId bel, PortPin pin) const;
+    PortType getBelPinType(BelId bel, PortPin pin) const;
+    std::vector<PortPin> getBelPins(BelId bel) const;
 
     WireId getWireByName(IdString name) const;
     IdString getWireName(WireId wire) const;
@@ -159,6 +165,7 @@ struct Arch : BaseCtx
     IdString getConflictingWireNet(WireId wire) const;
     DelayInfo getWireDelay(WireId wire) const { return DelayInfo(); }
     const std::vector<WireId> &getWires() const;
+    const std::vector<BelPin> &getWireBelPins(WireId wire) const;
 
     PipId getPipByName(IdString name) const;
     IdString getPipName(PipId pip) const;