Merge pull request #1008 from YosysHQ/gatecat/generic-addbelpin

generic: addBelPin with direction as an arg

3 files changed, 12 insertions, 25 deletions

diff --git a/generic/arch.cc b/generic/arch.cc
index 3df58c9b..9992e1cd 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -134,40 +134,20 @@ BelId Arch::addBel(IdStringList name, IdString type, Loc loc, bool gb, bool hidd
     return bel;
 }
 
-void Arch::addBelInput(BelId bel, IdString name, WireId wire)
-{
-    auto &bi = bel_info(bel);
-    NPNR_ASSERT(bi.pins.count(name) == 0);
-    PinInfo &pi = bi.pins[name];
-    pi.name = name;
-    pi.wire = wire;
-    pi.type = PORT_IN;
-
-    if (wire != WireId())
-        wire_info(wire).bel_pins.push_back(BelPin{bel, name});
-}
+void Arch::addBelInput(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_IN); }
 
-void Arch::addBelOutput(BelId bel, IdString name, WireId wire)
-{
-    auto &bi = bel_info(bel);
-    NPNR_ASSERT(bi.pins.count(name) == 0);
-    PinInfo &pi = bi.pins[name];
-    pi.name = name;
-    pi.wire = wire;
-    pi.type = PORT_OUT;
+void Arch::addBelOutput(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_OUT); }
 
-    if (wire != WireId())
-        wire_info(wire).bel_pins.push_back(BelPin{bel, name});
-}
+void Arch::addBelInout(BelId bel, IdString name, WireId wire) { addBelPin(bel, name, wire, PORT_INOUT); }
 
-void Arch::addBelInout(BelId bel, IdString name, WireId wire)
+void Arch::addBelPin(BelId bel, IdString name, WireId wire, PortType type)
 {
     auto &bi = bel_info(bel);
     NPNR_ASSERT(bi.pins.count(name) == 0);
     PinInfo &pi = bi.pins[name];
     pi.name = name;
     pi.wire = wire;
-    pi.type = PORT_INOUT;
+    pi.type = type;
 
     if (wire != WireId())
         wire_info(wire).bel_pins.push_back(BelPin{bel, name});
diff --git a/generic/arch.h b/generic/arch.h
index 157ff8af..688392da 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -200,6 +200,7 @@ struct Arch : BaseArch<ArchRanges>
     void addBelInput(BelId bel, IdString name, WireId wire);
     void addBelOutput(BelId bel, IdString name, WireId wire);
     void addBelInout(BelId bel, IdString name, WireId wire);
+    void addBelPin(BelId bel, IdString name, WireId wire, PortType type);
 
     WireId addWireAsBelInput(BelId bel, IdString name);
     WireId addWireAsBelOutput(BelId bel, IdString name);
diff --git a/generic/arch_pybindings.cc b/generic/arch_pybindings.cc
index e0a2f0f2..a5a0bed9 100644
--- a/generic/arch_pybindings.cc
+++ b/generic/arch_pybindings.cc
@@ -105,6 +105,12 @@ void arch_wrap_python(py::module &m)
     fn_wrapper_3a_v<Context, decltype(&Context::addBelInout), &Context::addBelInout, conv_from_str<BelId>,
                     conv_from_str<IdString>, conv_from_str<WireId>>::def_wrap(ctx_cls, "addBelInout", "bel"_a, "name"_a,
                                                                               "wire"_a);
+    fn_wrapper_4a_v<Context, decltype(&Context::addBelPin), &Context::addBelPin, conv_from_str<BelId>,
+                    conv_from_str<IdString>, conv_from_str<WireId>, pass_through<PortType>>::def_wrap(ctx_cls,
+                                                                                                      "addBelPin",
+                                                                                                      "bel"_a, "name"_a,
+                                                                                                      "wire"_a,
+                                                                                                      "type"_a);
 
     fn_wrapper_2a_v<Context, decltype(&Context::addGroupBel), &Context::addGroupBel, conv_from_str<IdStringList>,
                     conv_from_str<BelId>>::def_wrap(ctx_cls, "addGroupBel", "group"_a, "bel"_a);