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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-28 13:54:06 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-28 13:54:06 +0100 |
| commit | 796d6489953927105d3b0ed22308f29676b168fa (patch) | |
| tree | bc0f470642c0943713c441aa7c3e9e310cb23ccc /generic/synth | |
| parent | 50f87a6024859d197eefa8de0b0b616b1e03e239 (diff) | |
| parent | 0d43aff2682d91817ea4a1fb5dff6e169ae9a659 (diff) | |
| download | nextpnr-796d6489953927105d3b0ed22308f29676b168fa.tar.gz nextpnr-796d6489953927105d3b0ed22308f29676b168fa.tar.bz2 nextpnr-796d6489953927105d3b0ed22308f29676b168fa.zip | |
Merge remote-tracking branch 'origin/master' into mmicko/ecp5_gui
Diffstat (limited to 'generic/synth')
| -rw-r--r-- | generic/synth/cells_map.v | 4 | ||||
| -rw-r--r-- | generic/synth/prims.v | 28 |
2 files changed, 21 insertions, 11 deletions
diff --git a/generic/synth/cells_map.v b/generic/synth/cells_map.v index a6027534..1d0939e0 100644 --- a/generic/synth/cells_map.v +++ b/generic/synth/cells_map.v @@ -4,7 +4,9 @@ module \$lut (A, Y); input [WIDTH-1:0] A; output Y; - LUT #(.K(`LUT_K), .INIT(LUT)) _TECHMAP_REPLACE_ (.I(A), .Q(Y)); + localparam rep = 1<<(`LUT_K-WIDTH); + + LUT #(.K(`LUT_K), .INIT({rep{LUT}})) _TECHMAP_REPLACE_ (.I(A), .Q(Y)); endmodule module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule diff --git a/generic/synth/prims.v b/generic/synth/prims.v index 95fcfac7..ca445e6e 100644 --- a/generic/synth/prims.v +++ b/generic/synth/prims.v @@ -2,18 +2,27 @@ module LUT #( parameter K = 4, - parameter [2**K-1:0] INIT = 0, + parameter [2**K-1:0] INIT = 0 ) ( input [K-1:0] I, output Q ); - assign Q = INIT[I]; + wire [K-1:0] I_pd; + + genvar ii; + generate + for (ii = 0; ii < K; ii = ii + 1'b1) + assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii]; + endgenerate + + assign Q = INIT[I_pd]; endmodule module DFF ( input CLK, D, output reg Q ); + initial Q = 1'b0; always @(posedge CLK) Q <= D; endmodule @@ -25,17 +34,16 @@ module GENERIC_SLICE #( ) ( input CLK, input [K-1:0] I, + output F, output Q ); + wire f_wire; - wire lut_q; - LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(lut_q)); + LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire)); - generate if (FF_USED) - DFF dff_i(.CLK(CLK), .D(lut_q), .Q(Q)); - else - assign Q = lut_q; - endgenerate + DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q)); + + assign F = f_wire; endmodule module GENERIC_IOB #( @@ -56,4 +64,4 @@ module GENERIC_IOB #( generate if (INPUT_USED) assign O = PAD; endgenerate -endmodule
\ No newline at end of file +endmodule |
