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| author | David Shah <dave@ds0.me> | 2019-11-08 16:28:39 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-08 16:28:39 +0000 |
| commit | 6a335411da6eb54f0960eb514c5384e4ae60c3a7 (patch) | |
| tree | 0ff3e83dc88a2b59275136e098ba5e59ed473480 /generic/synth | |
| parent | caf7abdb8dd7ec97801fd13efc8ae132e637ecd3 (diff) | |
| parent | a4848f6902f81b6d3f2a36ab853922047e177288 (diff) | |
| download | nextpnr-6a335411da6eb54f0960eb514c5384e4ae60c3a7.tar.gz nextpnr-6a335411da6eb54f0960eb514c5384e4ae60c3a7.tar.bz2 nextpnr-6a335411da6eb54f0960eb514c5384e4ae60c3a7.zip | |
Merge pull request #350 from pepijndevos/newslice
Dedicated output for LUT in GENERIC_SLICE
Diffstat (limited to 'generic/synth')
| -rw-r--r-- | generic/synth/prims.v | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/generic/synth/prims.v b/generic/synth/prims.v index 95fcfac7..1148041c 100644 --- a/generic/synth/prims.v +++ b/generic/synth/prims.v @@ -25,17 +25,16 @@ module GENERIC_SLICE #( ) ( input CLK, input [K-1:0] I, + output F, output Q ); + wire f_wire; - wire lut_q; - LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(lut_q)); + LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire)); - generate if (FF_USED) - DFF dff_i(.CLK(CLK), .D(lut_q), .Q(Q)); - else - assign Q = lut_q; - endgenerate + DFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q)); + + assign F = f_wire; endmodule module GENERIC_IOB #( @@ -56,4 +55,4 @@ module GENERIC_IOB #( generate if (INPUT_USED) assign O = PAD; endgenerate -endmodule
\ No newline at end of file +endmodule |