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author | gatecat <gatecat@ds0.me> | 2021-02-19 10:39:57 +0000 |
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committer | gatecat <gatecat@ds0.me> | 2021-02-19 11:31:33 +0000 |
commit | 7922b3bfc4ef93b8f67194c05e1a236b4c83c3da (patch) | |
tree | b2b21259e030edd0adc7cc944322e3e9186d3a71 /fpga_interchange | |
parent | 8376db94a7519406444988be3628a4dadfb8d742 (diff) | |
download | nextpnr-7922b3bfc4ef93b8f67194c05e1a236b4c83c3da.tar.gz nextpnr-7922b3bfc4ef93b8f67194c05e1a236b4c83c3da.tar.bz2 nextpnr-7922b3bfc4ef93b8f67194c05e1a236b4c83c3da.zip |
Replace DelayInfo with DelayPair/DelayQuad
This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange')
-rw-r--r-- | fpga_interchange/arch.cc | 2 | ||||
-rw-r--r-- | fpga_interchange/arch.h | 18 | ||||
-rw-r--r-- | fpga_interchange/archdefs.h | 21 |
3 files changed, 5 insertions, 36 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index 71ba46e4..9bcd7f79 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -686,7 +686,7 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const return 0; } -bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const +bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const { // FIXME: Implement when adding timing-driven place and route. return false; diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 76497d6d..82a2788b 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -1127,12 +1127,7 @@ struct Arch : ArchAPI<ArchRanges> return w2n == wire_to_net.end() ? nullptr : w2n->second; } - DelayInfo getWireDelay(WireId wire) const override - { - DelayInfo delay; - delay.delay = 0; - return delay; - } + DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); } TileWireRange get_tile_wire_range(WireId wire) const { @@ -1279,7 +1274,7 @@ struct Arch : ArchAPI<ArchRanges> return canonical_wire(chip_info, pip.tile, loc_info(chip_info, pip).pip_data[pip.index].dst_index); } - DelayInfo getPipDelay(PipId pip) const override { return DelayInfo(); } + DelayQuad getPipDelay(PipId pip) const override { return DelayQuad(0); } DownhillPipRange getPipsDownhill(WireId wire) const override { @@ -1333,12 +1328,7 @@ struct Arch : ArchAPI<ArchRanges> delay_t getDelayEpsilon() const override { return 20; } delay_t getRipupDelayPenalty() const override { return 120; } float getDelayNS(delay_t v) const override { return v * 0.001; } - DelayInfo getDelayFromNS(float ns) const override - { - DelayInfo del; - del.delay = delay_t(ns * 1000); - return del; - } + delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); } uint32_t getDelayChecksum(delay_t v) const override { return v; } bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override; @@ -1363,7 +1353,7 @@ struct Arch : ArchAPI<ArchRanges> // Get the delay through a cell from one port to another, returning false // if no path exists. This only considers combinational delays, as required by the Arch API - bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const override; + bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override; // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override; // Get the TimingClockingInfo of a port diff --git a/fpga_interchange/archdefs.h b/fpga_interchange/archdefs.h index e280de55..75af6974 100644 --- a/fpga_interchange/archdefs.h +++ b/fpga_interchange/archdefs.h @@ -28,27 +28,6 @@ NEXTPNR_NAMESPACE_BEGIN typedef int delay_t; -struct DelayInfo -{ - delay_t delay = 0; - - delay_t minRaiseDelay() const { return delay; } - delay_t maxRaiseDelay() const { return delay; } - - delay_t minFallDelay() const { return delay; } - delay_t maxFallDelay() const { return delay; } - - delay_t minDelay() const { return delay; } - delay_t maxDelay() const { return delay; } - - DelayInfo operator+(const DelayInfo &other) const - { - DelayInfo ret; - ret.delay = this->delay + other.delay; - return ret; - } -}; - // ----------------------------------------------------------------------- struct BelId |