diff options
| author | gatecat <gatecat@ds0.me> | 2021-07-06 10:38:08 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-07-06 10:38:08 +0100 |
| commit | 31abefc8e49edce55fb42c99ac99b81e948d9004 (patch) | |
| tree | 11d7496a94275f54e98d566958890285e18a3104 /fpga_interchange | |
| parent | 6fe071ad1d47c363f665995ae774edcd547e022d (diff) | |
| download | nextpnr-31abefc8e49edce55fb42c99ac99b81e948d9004.tar.gz nextpnr-31abefc8e49edce55fb42c99ac99b81e948d9004.tar.bz2 nextpnr-31abefc8e49edce55fb42c99ac99b81e948d9004.zip | |
interchange: Allow pseudo pip wires to overlap with bound site wires on the same net
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange')
| -rw-r--r-- | fpga_interchange/arch.cc | 11 | ||||
| -rw-r--r-- | fpga_interchange/arch.h | 3 |
2 files changed, 5 insertions, 9 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index be40ddfd..901725d4 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -1518,11 +1518,6 @@ void Arch::remove_pip_pseudo_wires(PipId pip, NetInfo *net) // This wire is part of net->wires, make sure it has no pip, // but leave it alone. It will get cleaned up via // unbindWire. - if (wire_iter->second.pip != PipId() && wire_iter->second.pip != pip) { - log_error("Wire %s report source'd from pip %s, which is not %s\n", nameOfWire(wire), - nameOfPip(wire_iter->second.pip), nameOfPip(pip)); - } - NPNR_ASSERT(wire_iter->second.pip == PipId() || wire_iter->second.pip == pip); } else { // This wire is not in net->wires, update wire_to_net. #ifdef DEBUG_BINDING @@ -1756,12 +1751,12 @@ bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const NPNR_ASSERT(src != wire); NPNR_ASSERT(dst != wire); - NetInfo *net = getConflictingWireNet(wire); - if (net != nullptr) { + NetInfo *other_net = getConflictingWireNet(wire); + if (other_net != nullptr && other_net != net) { #ifdef DEBUG_BINDING if (getCtx()->verbose) { log_info("Pip %s is not available because wire %s is tied to net %s\n", getCtx()->nameOfPip(pip), - getCtx()->nameOfWire(wire), net->name.c_str(getCtx())); + getCtx()->nameOfWire(wire), other_net->name.c_str(getCtx())); } #endif return false; diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index b71b1d03..896a603a 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -576,7 +576,8 @@ struct Arch : ArchAPI<ArchRanges> const PipInfoPOD &pip_data = pip_info(chip_info, pip); for (int32_t wire_index : pip_data.pseudo_cell_wires) { wire.index = wire_index; - assign_net_to_wire(wire, net, "pseudo", /*require_empty=*/true); + if (getBoundWireNet(wire) != net) + assign_net_to_wire(wire, net, "pseudo", /*require_empty=*/true); } if (pip_data.pseudo_cell_wires.size() > 0) { |