Merge pull request #640 from litghost/inversion_logic

Initial inverter logic for FPGA interchange

1 files changed, 16 insertions, 0 deletions

diff --git a/fpga_interchange/site_routing_cache.cc b/fpga_interchange/site_routing_cache.cc
index f7321a46..e6f4dc70 100644
--- a/fpga_interchange/site_routing_cache.cc
+++ b/fpga_interchange/site_routing_cache.cc
@@ -31,14 +31,27 @@ void SiteRoutingSolution::store_solution(const SiteArch *ctx, const RouteNodeSto
     clear();
 
     solution_sinks.reserve(solutions.size());
+    inverted.reserve(solutions.size());
+    can_invert.reserve(solutions.size());
 
     for (size_t route : solutions) {
+        bool sol_inverted = false;
+        bool sol_can_invert = false;
+
         SiteWire wire = node_storage->get_node(route)->wire;
         solution_sinks.push_back(wire);
 
         solution_offsets.push_back(solution_storage.size());
         Node cursor = node_storage->get_node(route);
         while (cursor.has_parent()) {
+            if (ctx->isInverting(cursor->pip) && !sol_can_invert) {
+                sol_inverted = !sol_inverted;
+            }
+            if (ctx->canInvert(cursor->pip)) {
+                sol_inverted = false;
+                sol_can_invert = true;
+            }
+
             solution_storage.push_back(cursor->pip);
             Node parent = cursor.parent();
             NPNR_ASSERT(ctx->getPipDstWire(cursor->pip) == cursor->wire);
@@ -46,6 +59,9 @@ void SiteRoutingSolution::store_solution(const SiteArch *ctx, const RouteNodeSto
             cursor = parent;
         }
 
+        inverted.push_back(sol_inverted);
+        can_invert.push_back(sol_can_invert);
+
         NPNR_ASSERT(cursor->wire == driver);
     }