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| author | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-02-24 14:02:21 -0800 |
|---|---|---|
| committer | Keith Rothman <537074+litghost@users.noreply.github.com> | 2021-02-26 11:01:22 -0800 |
| commit | cfa449c3f3c5b151eb11ef79bc2cf571e98bbbed (patch) | |
| tree | 38d78928c17745e07689a9d6d4bfdfcdf4e36b1f /fpga_interchange/site_router.cc | |
| parent | 9cbfd0b967f5804472afbb91d8df92e69dffe659 (diff) | |
| download | nextpnr-cfa449c3f3c5b151eb11ef79bc2cf571e98bbbed.tar.gz nextpnr-cfa449c3f3c5b151eb11ef79bc2cf571e98bbbed.tar.bz2 nextpnr-cfa449c3f3c5b151eb11ef79bc2cf571e98bbbed.zip | |
Initial LUT rotation logic.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'fpga_interchange/site_router.cc')
| -rw-r--r-- | fpga_interchange/site_router.cc | 35 |
1 files changed, 30 insertions, 5 deletions
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc index 7232b635..56bce01a 100644 --- a/fpga_interchange/site_router.cc +++ b/fpga_interchange/site_router.cc @@ -747,17 +747,42 @@ bool SiteRouter::checkSiteRouting(const Context *ctx, const TileStatus &tile_sta return site_ok; } } - // + // FIXME: Populate "consumed_wires" with all VCC/GND tied in the site. // This will allow route_site to leverage site local constant sources. // // FIXME: Handle case where a constant is requested, but use of an // inverter is possible. This is the place to handle "bestConstant" // (e.g. route VCC's over GND's, etc). - // - // FIXME: Enable some LUT rotation! - // Default cell/bel pin map always uses high pins, which will generate - // conflicts where there are none!!! + auto tile_type_idx = ctx->chip_info->tiles[tile].type; + const std::vector<LutElement> &lut_elements = ctx->lut_elements.at(tile_type_idx); + std::vector<LutMapper> lut_mappers; + lut_mappers.reserve(lut_elements.size()); + for (size_t i = 0; i < lut_elements.size(); ++i) { + lut_mappers.push_back(LutMapper(lut_elements[i])); + } + + for (CellInfo *cell : cells_in_site) { + if (cell->lut_cell.pins.empty()) { + continue; + } + + BelId bel = cell->bel; + const auto &bel_data = bel_info(ctx->chip_info, bel); + if (bel_data.lut_element != -1) { + lut_mappers[bel_data.lut_element].cells.push_back(cell); + } + } + + for (LutMapper lut_mapper : lut_mappers) { + if (lut_mapper.cells.empty()) { + continue; + } + + if (!lut_mapper.remap_luts(ctx)) { + return false; + } + } SiteInformation site_info(ctx, cells_in_site); |