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| author | myrtle <gatecat@ds0.me> | 2022-05-13 09:09:50 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-05-13 09:09:50 +0100 |
| commit | 4ecbf6c6e941699413e0d0bba660fc9dc18efcfe (patch) | |
| tree | 4dc7868ffbb4d86e45fb5874e17b88d747e72bfc /fpga_interchange/site_lut_mapping_cache.cc | |
| parent | 41936fefac2b819ad77204f0ed64ba01e9138c2a (diff) | |
| parent | d75c45c63f444af0349463346101c9d7d7ae6283 (diff) | |
| download | nextpnr-4ecbf6c6e941699413e0d0bba660fc9dc18efcfe.tar.gz nextpnr-4ecbf6c6e941699413e0d0bba660fc9dc18efcfe.tar.bz2 nextpnr-4ecbf6c6e941699413e0d0bba660fc9dc18efcfe.zip | |
Merge pull request #985 from antmicro/interchange-lut-constants
[interchange] Tying unused LUT inputs according to architecture
Diffstat (limited to 'fpga_interchange/site_lut_mapping_cache.cc')
| -rw-r--r-- | fpga_interchange/site_lut_mapping_cache.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/fpga_interchange/site_lut_mapping_cache.cc b/fpga_interchange/site_lut_mapping_cache.cc index b7a71397..82832ed9 100644 --- a/fpga_interchange/site_lut_mapping_cache.cc +++ b/fpga_interchange/site_lut_mapping_cache.cc @@ -138,8 +138,8 @@ bool SiteLutMappingResult::apply(const SiteInformation &siteInfo) } // LUT data - // FIXME: Is there any other info that is being updated than vcc_pins ? - cellInfo->lut_cell.vcc_pins = std::move(cell.lutCell.vcc_pins); + // FIXME: Is there any other info that is being updated than pin_connections ? + cellInfo->lut_cell.pin_connections = std::move(cell.lutCell.pin_connections); } return true; |