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| author | gatecat <gatecat@ds0.me> | 2022-02-16 16:15:26 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-16 16:15:26 +0000 |
| commit | 25c47e5b7e12d232cac9408b7d6d339ee11793b7 (patch) | |
| tree | 7700f5ce4d8b40255aa54e08d2c4489e74b906ff /fpga_interchange/pseudo_pip_model.cc | |
| parent | 02e6d2dbca0433e6f873c6af635cee701e84f5f5 (diff) | |
| parent | 30fd86ce69fa65e89dec119e23b5bccb54de70a3 (diff) | |
| download | nextpnr-25c47e5b7e12d232cac9408b7d6d339ee11793b7.tar.gz nextpnr-25c47e5b7e12d232cac9408b7d6d339ee11793b7.tar.bz2 nextpnr-25c47e5b7e12d232cac9408b7d6d339ee11793b7.zip | |
Merge pull request #917 from YosysHQ/gatecat/netlist-i
refactor: New NetInfo and CellInfo constructors
Diffstat (limited to 'fpga_interchange/pseudo_pip_model.cc')
| -rw-r--r-- | fpga_interchange/pseudo_pip_model.cc | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/fpga_interchange/pseudo_pip_model.cc b/fpga_interchange/pseudo_pip_model.cc index 39718c65..7f2427c4 100644 --- a/fpga_interchange/pseudo_pip_model.cc +++ b/fpga_interchange/pseudo_pip_model.cc @@ -355,12 +355,11 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) NPNR_ASSERT(bel_data.lut_element != -1); - lut_thru_cells.emplace_back(); + lut_thru_cells.emplace_back(nullptr, IdString(), IdString(ctx->wire_lut->cell)); CellInfo &cell = lut_thru_cells.back(); cell.bel = bel; - cell.type = IdString(ctx->wire_lut->cell); NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1); cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0])); @@ -384,7 +383,7 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) continue; } - lut_cells.emplace_back(); + lut_cells.emplace_back(nullptr, IdString(), ctx->wire_lut ? IdString(ctx->wire_lut->cell) : IdString()); CellInfo &cell = lut_cells.back(); cell.bel.tile = tile; @@ -393,7 +392,6 @@ void PseudoPipModel::update_site(const Context *ctx, size_t site) if (ctx->wire_lut == nullptr) continue; - cell.type = IdString(ctx->wire_lut->cell); NPNR_ASSERT(ctx->wire_lut->input_pins.size() == 1); cell.lut_cell.pins.push_back(IdString(ctx->wire_lut->input_pins[0])); |