Add initial logic for handling dedicated interconnect situations.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

4 files changed, 42 insertions, 0 deletions

diff --git a/fpga_interchange/examples/ff/Makefile b/fpga_interchange/examples/ff/Makefile
new file mode 100644
index 00000000..c6118ff7
--- /dev/null
+++ b/fpga_interchange/examples/ff/Makefile
@@ -0,0 +1,8 @@
+DESIGN := ff
+DESIGN_TOP := top
+PACKAGE := csg324
+
+include ../template.mk
+
+build/ff.json: ff.v | build
+	yosys -c run.tcl
diff --git a/fpga_interchange/examples/ff/ff.v b/fpga_interchange/examples/ff/ff.v
new file mode 100644
index 00000000..1c271042
--- /dev/null
+++ b/fpga_interchange/examples/ff/ff.v
@@ -0,0 +1,11 @@
+module top(input clk, input d, input r, output reg q);
+
+always @(posedge clk)
+begin
+    if(r)
+        q <= 1'b0;
+    else
+        q <= d;
+end
+
+endmodule
diff --git a/fpga_interchange/examples/ff/ff.xdc b/fpga_interchange/examples/ff/ff.xdc
new file mode 100644
index 00000000..3c132f1d
--- /dev/null
+++ b/fpga_interchange/examples/ff/ff.xdc
@@ -0,0 +1,9 @@
+set_property PACKAGE_PIN P17 [get_ports clk]
+set_property PACKAGE_PIN N15 [get_ports d]
+set_property PACKAGE_PIN N16 [get_ports r]
+set_property PACKAGE_PIN M17 [get_ports q]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports d]
+set_property IOSTANDARD LVCMOS33 [get_ports r]
+set_property IOSTANDARD LVCMOS33 [get_ports q]
diff --git a/fpga_interchange/examples/ff/run.tcl b/fpga_interchange/examples/ff/run.tcl
new file mode 100644
index 00000000..726d86eb
--- /dev/null
+++ b/fpga_interchange/examples/ff/run.tcl
@@ -0,0 +1,14 @@
+yosys -import
+
+read_verilog ff.v
+
+synth_xilinx -nolutram -nowidelut -nosrl -nocarry -nodsp
+
+# opt_expr -undriven makes sure all nets are driven, if only by the $undef
+# net.
+opt_expr -undriven
+opt_clean
+
+setundef -zero -params
+
+write_json build/ff.json