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| author | gatecat <gatecat@ds0.me> | 2021-06-30 13:00:12 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-06-30 13:00:12 +0100 |
| commit | 152c41c3ac4541ddfa2147be1ac89f9d0eaf5c6e (patch) | |
| tree | 8bf5a86b5b473e535686ac836e53c44eff3ccdab /fpga_interchange/archdefs.h | |
| parent | 91b998bb11e4bce04ecd6e2a81119714fb4640ae (diff) | |
| parent | b3882f8324507ed503ff481abda3dffded0d0b67 (diff) | |
| download | nextpnr-152c41c3ac4541ddfa2147be1ac89f9d0eaf5c6e.tar.gz nextpnr-152c41c3ac4541ddfa2147be1ac89f9d0eaf5c6e.tar.bz2 nextpnr-152c41c3ac4541ddfa2147be1ac89f9d0eaf5c6e.zip | |
Merge pull request #739 from YosysHQ/gatecat/usp-io-macro
interchange: Place entire IO macro based on routeability
Diffstat (limited to 'fpga_interchange/archdefs.h')
| -rw-r--r-- | fpga_interchange/archdefs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga_interchange/archdefs.h b/fpga_interchange/archdefs.h index 057de934..4a196c29 100644 --- a/fpga_interchange/archdefs.h +++ b/fpga_interchange/archdefs.h @@ -120,6 +120,7 @@ struct ArchCellInfo dict<IdString, std::vector<IdString>> cell_bel_pins; dict<IdString, std::vector<IdString>> masked_cell_bel_pins; pool<IdString> const_ports; + IdString macro_parent = IdString(); LutCell lut_cell; }; |