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| author | gatecat <gatecat@ds0.me> | 2021-04-20 11:33:51 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-04-20 11:33:51 +0100 |
| commit | 95698827b876c5afa368ed8746d155d68a8b6bbf (patch) | |
| tree | 2af311119f6ff54222020691248d0509ccd9ad69 /fpga_interchange/arch.h | |
| parent | 6fbefb8f1388dbb2bfe059624f7cb76ee9a81c5e (diff) | |
| parent | 0e6955a08dabf744cb57e6c440ff3ab62fd2a507 (diff) | |
| download | nextpnr-95698827b876c5afa368ed8746d155d68a8b6bbf.tar.gz nextpnr-95698827b876c5afa368ed8746d155d68a8b6bbf.tar.bz2 nextpnr-95698827b876c5afa368ed8746d155d68a8b6bbf.zip | |
Merge pull request #682 from YosysHQ/gatecat/default-cellpins
interchange: Handle missing/disconnected cell pins
Diffstat (limited to 'fpga_interchange/arch.h')
| -rw-r--r-- | fpga_interchange/arch.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 9b369c92..da620699 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -1100,6 +1100,9 @@ struct Arch : ArchAPI<ArchRanges> void unmask_bel_pins(); void explain_bel_status(BelId bel) const; + + const DefaultCellConnsPOD *get_default_conns(IdString cell_type) const; + void pack_default_conns(); }; NEXTPNR_NAMESPACE_END |