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authorgatecat <gatecat@ds0.me>2021-12-19 18:46:10 +0000
committerGitHub <noreply@github.com>2021-12-19 18:46:10 +0000
commit62a3e093856063180526b7189d5e711a98036fa0 (patch)
treed03ba5688367cb476a06b19d04ca78d0352afce3 /fpga_interchange/arch.h
parent56d550733346000584b9490fac0953fe07124035 (diff)
parentddb084e9a8a0cba10536951236cde824526e8071 (diff)
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Merge pull request #883 from YosysHQ/gatecat/new-predictdelay
archapi: Use arbitrary rather than actual placement in predictDelay [breaking change]
Diffstat (limited to 'fpga_interchange/arch.h')
-rw-r--r--fpga_interchange/arch.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h
index 482bf911..8bb2e2d1 100644
--- a/fpga_interchange/arch.h
+++ b/fpga_interchange/arch.h
@@ -700,7 +700,7 @@ struct Arch : ArchAPI<ArchRanges>
// -------------------------------------------------
delay_t estimateDelay(WireId src, WireId dst) const final;
- delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const final;
+ delay_t predictDelay(BelId src_bel, IdString src_pin, BelId dst_bel, IdString dst_pin) const final;
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const final;
delay_t getDelayEpsilon() const final { return 20; }
delay_t getRipupDelayPenalty() const final { return 120; }