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| author | gatecat <gatecat@ds0.me> | 2021-03-23 16:59:35 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-03-23 16:59:35 +0000 |
| commit | 2300d81c3c3874801176121b1a97446146ec6efd (patch) | |
| tree | cd4fb58c4a239a360c65f45972e621381b908e42 /fpga_interchange/arch.h | |
| parent | 8c85e648dfdb73d69d4adbc6420e706d21d61f93 (diff) | |
| parent | 831b94cdac7af66e11d0e3d67fa3bbff29678d05 (diff) | |
| download | nextpnr-2300d81c3c3874801176121b1a97446146ec6efd.tar.gz nextpnr-2300d81c3c3874801176121b1a97446146ec6efd.tar.bz2 nextpnr-2300d81c3c3874801176121b1a97446146ec6efd.zip | |
Merge pull request #640 from litghost/inversion_logic
Initial inverter logic for FPGA interchange
Diffstat (limited to 'fpga_interchange/arch.h')
| -rw-r--r-- | fpga_interchange/arch.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/fpga_interchange/arch.h b/fpga_interchange/arch.h index 8e08f17b..1f0eb80d 100644 --- a/fpga_interchange/arch.h +++ b/fpga_interchange/arch.h @@ -1028,6 +1028,12 @@ struct Arch : ArchAPI<ArchRanges> return wire_data.site != -1; } + // Does this pip always invert its signal? + bool is_inverting(PipId pip) const; + + // Can this pip optional invert its signal? + bool can_invert(PipId pip) const; + void merge_constant_nets(); void report_invalid_bel(BelId bel, CellInfo *cell) const; |