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| author | myrtle <gatecat@ds0.me> | 2022-08-10 11:25:34 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-08-10 11:25:34 +0100 |
| commit | 66722096edaff35f1620ebfc9acaab13ae149377 (patch) | |
| tree | 8b189e44b65afabfaddb3402ab8aac544df9ba83 /fpga_interchange/arch.cc | |
| parent | 06ce27ed38279cfa3455e248ea2b2c773cdf6324 (diff) | |
| parent | 77c82b0fbf15892b0c8222bac89564f3f024493e (diff) | |
| download | nextpnr-66722096edaff35f1620ebfc9acaab13ae149377.tar.gz nextpnr-66722096edaff35f1620ebfc9acaab13ae149377.tar.bz2 nextpnr-66722096edaff35f1620ebfc9acaab13ae149377.zip | |
Merge pull request #1010 from YosysHQ/gatecat/idf
refactor: id(stringf(...)) to new idf(...) helper
Diffstat (limited to 'fpga_interchange/arch.cc')
| -rw-r--r-- | fpga_interchange/arch.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index 6a7c4fe1..3ce9f79e 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -907,7 +907,7 @@ static void prepare_sites_for_routing(Context *ctx) // We can't rely on bel pins not clashing with cell names (for Xilinx they use different naming schemes, for // Nexus they are the same) so add a prefix to the bel pin name to disambiguate it - IdString cell_pin = ctx->id(stringf("%s_PHYS", ctx->nameOf(bel_pin))); + IdString cell_pin = ctx->idf("%s_PHYS", ctx->nameOf(bel_pin)); PortInfo port_info; port_info.name = cell_pin; |