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authorDavid Shah <davey1576@gmail.com>2018-09-30 17:42:47 +0100
committerDavid Shah <davey1576@gmail.com>2018-09-30 17:42:47 +0100
commit9218d2e56b5d06a57f80e7270b1538d134f8a6fa (patch)
treefdb3c07512b31734d5f7b04c50c4b2122ff7624a /ecp5
parentfef29d87626d9030f54afafa92db744ea9f21741 (diff)
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ecp5: Relative placement and bitstream gen for carries
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ecp5')
-rw-r--r--ecp5/bitstream.cc17
-rw-r--r--ecp5/cells.cc2
-rw-r--r--ecp5/pack.cc20
3 files changed, 37 insertions, 2 deletions
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index f04b1269..5e851fbf 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -256,7 +256,22 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
}
- // TODO: CLKMUX, CEMUX, carry
+
+ if (str_or_default(ci->params, ctx->id("MODE"), "LOGIC") == "CCU2") {
+ cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0",
+ str_or_default(ci->params, ctx->id("INJECT1_0"), "YES"));
+ cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1",
+ str_or_default(ci->params, ctx->id("INJECT1_1"), "YES"));
+ }
+
+ // Tie unused inputs high
+ for (auto input : {id_A0, id_B0, id_C0, id_D0, id_A1, id_B1, id_C1, id_D1}) {
+ if (ci->ports.find(input) == ci->ports.end() || ci->ports.at(input).net == nullptr) {
+ cc.tiles[tname].add_enum(slice + "." + input.str(ctx) + "MUX", "1");
+ }
+ }
+
+ // TODO: CLKMUX
} else if (ci->type == ctx->id("TRELLIS_IO")) {
std::string pio = ctx->locInfo(bel)->bel_data[bel.index].name.get();
std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index 4a83bb30..7e101ab2 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -213,7 +213,7 @@ void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index)
void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc)
{
- lc->params[ctx->id("MODE")] = "CCU2C";
+ lc->params[ctx->id("MODE")] = "CCU2";
lc->params[ctx->id("LUT0_INITVAL")] = str_or_default(ccu->params, ctx->id("INIT0"), "0");
lc->params[ctx->id("LUT1_INITVAL")] = str_or_default(ccu->params, ctx->id("INIT1"), "0");
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 7a7e0dda..2f84cd02 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -532,6 +532,21 @@ class Ecp5Packer
cell_count++;
}
}
+
+ // Relative chain placement
+ for (auto &chain : all_chains) {
+ chain.cells.at(0)->constr_abs_z = true;
+ chain.cells.at(0)->constr_z = 0;
+ for (int i = 1; i < int(chain.cells.size()); i++) {
+ chain.cells.at(i)->constr_x = (i / 4);
+ chain.cells.at(i)->constr_y = 0;
+ chain.cells.at(i)->constr_z = i % 4;
+ chain.cells.at(i)->constr_abs_z = true;
+ chain.cells.at(i)->constr_parent = chain.cells.at(0);
+ chain.cells.at(0)->constr_children.push_back(chain.cells.at(i));
+ }
+ }
+
flush_cells();
}
@@ -650,6 +665,10 @@ class Ecp5Packer
} else if (is_ff(ctx, uc) && user.port == ctx->id("CE")) {
uc->params[ctx->id("CEMUX")] = constval ? "1" : "0";
uc->ports[user.port].net = nullptr;
+ } else if (is_carry(ctx, uc) && constval &&
+ (user.port == id_A0 || user.port == id_A1 || user.port == id_B0 || user.port == id_B1 ||
+ user.port == id_C0 || user.port == id_C1 || user.port == id_D0 || user.port == id_D1)) {
+ uc->ports[user.port].net = nullptr;
} else if (is_ff(ctx, uc) && user.port == ctx->id("LSR") &&
((!constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "LSR") ||
(constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "INV"))) {
@@ -724,6 +743,7 @@ class Ecp5Packer
{
pack_io();
pack_constants();
+ pack_carries();
find_lutff_pairs();
pack_lut5s();
pair_luts();