Merge pull request #236 from YosysHQ/ddrn

ecp5: Support for advanced IO functionality

10 files changed, 1099 insertions, 15 deletions

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 23cdea3b..7de5c7aa 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -746,6 +746,29 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
             return TMG_GEN_CLOCK;
         else
             NPNR_ASSERT_FALSE("bad clkdiv port");
+    } else if (cell->type == id_DQSBUFM) {
+        if (port == id_READ0 || port == id_READ1) {
+            clockInfoCount = 1;
+            return TMG_REGISTER_INPUT;
+        } else if (port == id_DATAVALID) {
+            clockInfoCount = 1;
+            return TMG_REGISTER_OUTPUT;
+        } else if (port == id_SCLK || port == id_ECLK || port == id_DQSI) {
+            return TMG_CLOCK_INPUT;
+        } else if (port == id_DQSR90 || port == id_DQSW || port == id_DQSW270) {
+            return TMG_GEN_CLOCK;
+        }
+        return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
+    } else if (cell->type == id_DDRDLL) {
+        if (port == id_CLK)
+            return TMG_CLOCK_INPUT;
+        return (cell->ports.at(port).type == PORT_OUT) ? TMG_STARTPOINT : TMG_ENDPOINT;
+    } else if (cell->type == id_TRELLIS_ECLKBUF) {
+        return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
+    } else if (cell->type == id_ECLKSYNCB) {
+        if (cell->ports.at(port).name == id_STOP)
+            return TMG_ENDPOINT;
+        return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
     } else {
         log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this),
                   cell->name.c_str(this));
@@ -829,6 +852,16 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
             info.setup = getDelayFromNS(0.1);
             info.hold = getDelayFromNS(0);
         }
+    } else if (cell->type == id_DQSBUFM) {
+        info.clock_port = id_SCLK;
+        if (port == id_DATAVALID) {
+            info.clockToQ = getDelayFromNS(0.2);
+        } else if (port == id_READ0 || port == id_READ1) {
+            info.setup = getDelayFromNS(0.5);
+            info.hold = getDelayFromNS(-0.4);
+        } else {
+            NPNR_ASSERT_FALSE("unknown DQSBUFM register port");
+        }
     }
     return info;
 }
@@ -850,4 +883,41 @@ GlobalInfoPOD Arch::globalInfoAtLoc(Location loc)
     return chip_info->location_glbinfo[locidx];
 }
 
+bool Arch::getPIODQSGroup(BelId pio, bool &dqsright, int &dqsrow)
+{
+    for (int i = 0; i < chip_info->num_pios; i++) {
+        if (Location(chip_info->pio_info[i].abs_loc) == pio.location && chip_info->pio_info[i].bel_index == pio.index) {
+            int dqs = chip_info->pio_info[i].dqsgroup;
+            if (dqs == -1)
+                return false;
+            else {
+                dqsright = (dqs & 2048) != 0;
+                dqsrow = dqs & 0x1FF;
+                return true;
+            }
+        }
+    }
+    NPNR_ASSERT_FALSE("failed to find PIO");
+}
+
+BelId Arch::getDQSBUF(bool dqsright, int dqsrow)
+{
+    BelId bel;
+    bel.location.y = dqsrow;
+    bel.location.x = (dqsright ? (chip_info->width - 1) : 0);
+    for (int i = 0; i < locInfo(bel)->num_bels; i++) {
+        auto &bd = locInfo(bel)->bel_data[i];
+        if (bd.type == id_DQSBUFM.index) {
+            bel.index = i;
+            return bel;
+        }
+    }
+    NPNR_ASSERT_FALSE("failed to find DQSBUF");
+}
+
+WireId Arch::getBankECLK(int bank, int eclk)
+{
+    return getWireByLocAndBasename(Location(0, 0), "G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(eclk));
+}
+
 NEXTPNR_NAMESPACE_END
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 713c320e..6a2f2bf5 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -103,7 +103,7 @@ NPNR_PACKED_STRUCT(struct PIOInfoPOD {
     int32_t bel_index;
     RelPtr<char> function_name;
     int16_t bank;
-    int16_t padding;
+    int16_t dqsgroup;
 });
 
 NPNR_PACKED_STRUCT(struct PackagePinPOD {
@@ -1006,6 +1006,10 @@ struct Arch : BaseCtx
 
     GlobalInfoPOD globalInfoAtLoc(Location loc);
 
+    bool getPIODQSGroup(BelId pio, bool &dqsright, int &dqsrow);
+    BelId getDQSBUF(bool dqsright, int dqsrow);
+    WireId getBankECLK(int bank, int eclk);
+
     // Apply LPF constraints to the context
     bool applyLPF(std::string filename, std::istream &in);
 
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index ccaafdb6..a9c82524 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -619,7 +619,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
     }
     // Find bank voltages
     std::unordered_map<int, IOVoltage> bankVcc;
-    std::unordered_map<int, bool> bankLvds;
+    std::unordered_map<int, bool> bankLvds, bankVref;
 
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
@@ -628,7 +628,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
             std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
 
-            if (dir != "INPUT") {
+            if (dir != "INPUT" || is_referenced(ioType_from_str(iotype))) {
                 IOVoltage vcc = get_vccio(ioType_from_str(iotype));
                 if (bankVcc.find(bank) != bankVcc.end()) {
                     // TODO: strong and weak constraints
@@ -644,6 +644,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
 
             if (iotype == "LVDS")
                 bankLvds[bank] = true;
+            if ((dir == "INPUT" || dir == "BIDIR") && is_referenced(ioType_from_str(iotype)))
+                bankVref[bank] = true;
         }
     }
 
@@ -655,17 +657,67 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                 std::string type = tile.second;
                 if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") {
                     int bank = std::stoi(type.substr(7));
-                    if (bankVcc.find(bank) != bankVcc.end())
-                        cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
+                    if (bankVcc.find(bank) != bankVcc.end()) {
+                        if (bankVcc[bank] == IOVoltage::VCC_1V35)
+                            cc.tiles[tile.first].add_enum("BANK.VCCIO", "1V2");
+                        else
+                            cc.tiles[tile.first].add_enum("BANK.VCCIO", iovoltage_to_str(bankVcc[bank]));
+                    }
                     if (bankLvds[bank]) {
                         cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
                         cc.tiles[tile.first].add_enum("BANK.LVDSO", "ON");
                     }
+                    if (bankVref[bank]) {
+                        cc.tiles[tile.first].add_enum("BANK.DIFF_REF", "ON");
+                        cc.tiles[tile.first].add_enum("BANK.VREF", "ON");
+                    }
                 }
             }
         }
     }
 
+    // Create dummy outputs used as Vref input buffer for banks where Vref is used
+    for (auto bv : bankVref) {
+        if (!bv.second)
+            continue;
+        BelId vrefIO = ctx->getPioByFunctionName(fmt_str("VREF1_" << bv.first));
+        if (vrefIO == BelId())
+            log_error("unable to find VREF input for bank %d\n", bv.first);
+        if (!ctx->checkBelAvail(vrefIO)) {
+            CellInfo *bound = ctx->getBoundBelCell(vrefIO);
+            if (bound != nullptr)
+                log_error("VREF pin %s of bank %d is occupied by IO '%s'\n", ctx->getBelPackagePin(vrefIO).c_str(),
+                          bv.first, bound->name.c_str(ctx));
+            else
+                log_error("VREF pin %s of bank %d is unavailable\n", ctx->getBelPackagePin(vrefIO).c_str(), bv.first);
+        }
+        log_info("Using pin %s as VREF for bank %d\n", ctx->getBelPackagePin(vrefIO).c_str(), bv.first);
+        std::string pio_tile = get_pio_tile(ctx, vrefIO);
+
+        std::string iotype;
+        switch (bankVcc[bv.first]) {
+        case IOVoltage::VCC_1V2:
+            iotype = "HSUL12";
+            break;
+        case IOVoltage::VCC_1V35:
+            iotype = "SSTL18_I";
+            break;
+        case IOVoltage::VCC_1V5:
+            iotype = "SSTL18_I";
+            break;
+        case IOVoltage::VCC_1V8:
+            iotype = "SSTL18_I";
+            break;
+        default:
+            log_error("Referenced inputs are not supported with bank VccIO of %s.\n",
+                      iovoltage_to_str(bankVcc[bv.first]).c_str());
+        }
+
+        std::string pio = ctx->locInfo(vrefIO)->bel_data[vrefIO.index].name.get();
+        cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", "OUTPUT_" + iotype);
+        cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
+    }
+
     // Configure slices
     for (auto &cell : ctx->cells) {
         CellInfo *ci = cell.second.get();
@@ -768,9 +820,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                 // cc.tiles[pic_tile].add_enum(other + ".BASE_TYPE", "_NONE_");
                 cc.tiles[pio_tile].add_enum(other + ".PULLMODE", "NONE");
                 cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
+            } else if (is_referenced(ioType_from_str(iotype))) {
+                cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
             }
             if (dir != "INPUT" &&
-                (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr)) {
+                (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr) &&
+                (ci->ports.find(ctx->id("IOLTO")) == ci->ports.end() ||
+                 ci->ports.at(ctx->id("IOLTO")).net == nullptr)) {
                 // Tie tristate low if unconnected for outputs or bidir
                 std::string jpt = fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/JPADDT" << pio.back());
                 WireId jpt_wire = ctx->getWireByName(ctx->id(jpt));
@@ -781,13 +837,37 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
                 std::string cib_wirename = ctx->locInfo(cib_wire)->wire_data[cib_wire.index].name.get();
                 cc.tiles[cib_tile].add_enum("CIB." + cib_wirename + "MUX", "0");
             }
-            if (dir == "INPUT" && !is_differential(ioType_from_str(iotype))) {
+            if (dir == "INPUT" && !is_differential(ioType_from_str(iotype)) &&
+                !is_referenced(ioType_from_str(iotype))) {
                 cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", "ON");
             }
-            if (ci->attrs.count(ctx->id("SLEWRATE")))
+            if (ci->attrs.count(ctx->id("SLEWRATE")) && !is_referenced(ioType_from_str(iotype)))
                 cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, ctx->id("SLEWRATE"), "SLOW"));
             if (ci->attrs.count(ctx->id("PULLMODE")))
                 cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, ctx->id("PULLMODE"), "NONE"));
+            if (ci->attrs.count(ctx->id("DIFFRESISTOR")))
+                cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR",
+                                            str_or_default(ci->attrs, ctx->id("DIFFRESISTOR"), "OFF"));
+            if (ci->attrs.count(ctx->id("TERMINATION"))) {
+                auto vccio = get_vccio(ioType_from_str(iotype));
+                switch (vccio) {
+                case IOVoltage::VCC_1V8:
+                    cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V8",
+                                                str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+                    break;
+                case IOVoltage::VCC_1V5:
+                    cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V5",
+                                                str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+                    break;
+                case IOVoltage::VCC_1V35:
+                    cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V35",
+                                                str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+                    break;
+                default:
+                    log_error("TERMINATION is not supported with Vcc = %s (on PIO %s)\n",
+                              iovoltage_to_str(vccio).c_str(), ci->name.c_str(ctx));
+                }
+            }
             std::string datamux_oddr = str_or_default(ci->params, ctx->id("DATAMUX_ODDR"), "PADDO");
             if (datamux_oddr != "PADDO")
                 cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_ODDR", datamux_oddr);
@@ -1190,6 +1270,56 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
             std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
             cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, ctx->id("DIV"), "2.0"));
             cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+        } else if (ci->type == id_TRELLIS_ECLKBUF) {
+        } else if (ci->type == id_DQSBUFM) {
+            Loc loc = ctx->getBelLocation(ci->bel);
+            bool l = loc.x < 10;
+            std::string pic = l ? "PICL" : "PICR";
+            TileGroup tg;
+            tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y - 2, loc.x, pic + "1_DQS0"));
+            tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y - 1, loc.x, pic + "2_DQS1"));
+            tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, pic + "0_DQS2"));
+            tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y + 1, loc.x, pic + "1_DQS3"));
+            tg.config.add_enum("DQS.MODE", "DQSBUFM");
+            tg.config.add_enum("DQS.DQS_LI_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS"));
+            tg.config.add_enum("DQS.DQS_LO_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS"));
+            int li_del_value = int_or_default(ci->params, ctx->id("DQS_LI_DEL_VAL"), 0);
+            if (str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS") == "MINUS")
+                li_del_value = (256 - li_del_value) & 0xFF;
+            int lo_del_value = int_or_default(ci->params, ctx->id("DQS_LO_DEL_VAL"), 0);
+            if (str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS") == "MINUS")
+                lo_del_value = (256 - lo_del_value) & 0xFF;
+            tg.config.add_word("DQS.DQS_LI_DEL_VAL", int_to_bitvector(li_del_value, 8));
+            tg.config.add_word("DQS.DQS_LO_DEL_VAL", int_to_bitvector(lo_del_value, 8));
+            tg.config.add_enum("DQS.WRLOADN_USED", get_net_or_empty(ci, id_WRLOADN) != nullptr ? "YES" : "NO");
+            tg.config.add_enum("DQS.RDLOADN_USED", get_net_or_empty(ci, id_RDLOADN) != nullptr ? "YES" : "NO");
+            tg.config.add_enum("DQS.PAUSE_USED", get_net_or_empty(ci, id_PAUSE) != nullptr ? "YES" : "NO");
+            tg.config.add_enum("DQS.READ_USED",
+                               (get_net_or_empty(ci, id_READ0) != nullptr || get_net_or_empty(ci, id_READ1) != nullptr)
+                                       ? "YES"
+                                       : "NO");
+            tg.config.add_enum("DQS.DDRDEL", get_net_or_empty(ci, id_DDRDEL) != nullptr ? "DDRDEL" : "0");
+            tg.config.add_enum("DQS.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+            cc.tilegroups.push_back(tg);
+        } else if (ci->type == id_ECLKSYNCB) {
+            Loc loc = ctx->getBelLocation(ci->bel);
+            bool r = loc.x > 5;
+            std::string eclksync = ctx->locInfo(bel)->bel_data[bel.index].name.get();
+            std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
+            if (get_net_or_empty(ci, id_STOP) != nullptr)
+                cc.tiles[tile].add_enum(eclksync + ".MODE", "ECLKSYNCB");
+        } else if (ci->type == id_DDRDLL) {
+            Loc loc = ctx->getBelLocation(ci->bel);
+            bool u = loc.y<15, r = loc.x> 15;
+            std::string tiletype = fmt_str("DDRDLL_" << (u ? 'U' : 'L') << (r ? 'R' : 'L'));
+            if (ctx->args.type == ArchArgs::LFE5U_25F || ctx->args.type == ArchArgs::LFE5UM_25F ||
+                ctx->args.type == ArchArgs::LFE5UM5G_25F)
+                tiletype += "A";
+            std::string tile = ctx->getTileByType(tiletype);
+            cc.tiles[tile].add_enum("DDRDLL.MODE", "DDRDLLA");
+            cc.tiles[tile].add_enum("DDRDLL.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+            cc.tiles[tile].add_enum("DDRDLL.FORCE_MAX_DELAY",
+                                    str_or_default(ci->params, ctx->id("FORCE_MAX_DELAY"), "NO"));
         } else {
             NPNR_ASSERT_FALSE("unsupported cell type");
         }
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index a8e92083..38bcc17c 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -201,6 +201,9 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
         }
         // Just copy ports from the Bel
         copy_bel_ports();
+    } else if (type == id_TRELLIS_ECLKBUF) {
+        add_port(ctx, new_cell.get(), "ECLKI", PORT_IN);
+        add_port(ctx, new_cell.get(), "ECLKO", PORT_OUT);
     } else {
         log_error("unable to create ECP5 cell of type %s", type.c_str(ctx));
     }
diff --git a/ecp5/cells.h b/ecp5/cells.h
index dcef99e3..e66f8f21 100644
--- a/ecp5/cells.h
+++ b/ecp5/cells.h
@@ -46,6 +46,17 @@ inline bool is_pfumx(const BaseCtx *ctx, const CellInfo *cell) { return cell->ty
 
 inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("L6MUX21"); }
 
+inline bool is_iologic_input_cell(const BaseCtx *ctx, const CellInfo *cell)
+{
+    return cell->type == ctx->id("IDDRX1F") || cell->type == ctx->id("IDDRX2F") || cell->type == ctx->id("IDDR71B") ||
+           cell->type == ctx->id("IDDRX2DQA");
+}
+inline bool is_iologic_output_cell(const BaseCtx *ctx, const CellInfo *cell)
+{
+    return cell->type == ctx->id("ODDRX1F") || cell->type == ctx->id("ODDRX2F") || cell->type == ctx->id("ODDR71B") ||
+           cell->type == ctx->id("ODDRX2DQA") || cell->type == ctx->id("ODDRX2DQSB") || cell->type == ctx->id("OSHX2A");
+}
+
 void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool driven_by_lut);
 void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index);
 void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc);
diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index 6ba453c7..8a3179b6 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -1280,3 +1280,5 @@ X(BURSTDET)
 X(RDCFLAG)
 X(WRCFLAG)
 X(SCLK)
+
+X(TRELLIS_ECLKBUF)
\ No newline at end of file
diff --git a/ecp5/docs/primitives.md b/ecp5/docs/primitives.md
new file mode 100644
index 00000000..aa37f3e5
--- /dev/null
+++ b/ecp5/docs/primitives.md
@@ -0,0 +1,47 @@
+# nextpnr-ecp5 Primitive Support List
+
+nextpnr-ecp5 currently supports the following primitives:
+ 
+ - **ALU54B** (limited support, must be manually placed)
+ - **CCU2C**
+ - **CLKDIVF**
+ - **DCUA**
+ - **DDRDLLA**
+ - **DELAYF**
+ - **DELAYG**
+ - **DP16KD**
+ - **DQSBUFM**
+ - **DTR**
+ - **ECLKSYNCB**
+ - **EHXPLLL**
+ - **EXTREFB**
+ - **GSR**
+ - **IDDR71B**
+ - **IDDRX1F**
+ - **IDDRX2DQA**
+ - **IDDRX2F**
+ - **IOLOGIC**
+ - **JTAGG** (untested)
+ - **L6MUX21**
+ - **LUT4**
+ - **MULT18X18D** (cascade functionality not supported)
+ - **ODDR71B**
+ - **ODDRX1F**
+ - **ODDRX2DQA**
+ - **ODDRX2DQSB**
+ - **ODDRX2F**
+ - **OSCG**
+ - **OSHX2A**
+ - **PCSCLKDIV**
+ - **PFUMX**
+ - **SEDGA** (untested)
+ - **SIOLOGIC**
+ - **TRELLIS_DPR16X4**
+ - **TRELLIS_ECLKBUF**
+ - **TRELLIS_FF**
+ - **TRELLIS_IO**
+ - **TRELLIS_SLICE**
+ - **TSHX2DQA**
+ - **TSHX2DQSA**
+ - **USRMCLK** (untested)
+
diff --git a/ecp5/lpf.cc b/ecp5/lpf.cc
index 4bde660e..df3687cf 100644
--- a/ecp5/lpf.cc
+++ b/ecp5/lpf.cc
@@ -60,8 +60,31 @@ bool Arch::applyLPF(std::string filename, std::istream &in)
                     words.push_back(tmp);
                 if (words.size() >= 0) {
                     std::string verb = words.at(0);
-                    if (verb == "BLOCK" || verb == "SYSCONFIG" || verb == "FREQUENCY") {
+                    if (verb == "BLOCK" || verb == "SYSCONFIG") {
                         log_warning("    ignoring unsupported LPF command '%s'\n", command.c_str());
+                    } else if (verb == "FREQUENCY") {
+                        std::string etype = words.at(1);
+                        if (etype == "PORT" || etype == "NET") {
+                            std::string target = words.at(2);
+                            if (target.at(0) == '\"') {
+                                NPNR_ASSERT(target.back() == '\"');
+                                target = target.substr(1, target.length() - 2);
+                            }
+                            float freq = std::stof(words.at(3));
+                            std::string unit = words.at(4);
+                            if (unit == "MHz")
+                                ;
+                            else if (unit == "kHz")
+                                freq /= 1.0e3;
+                            else if (unit == "Hz")
+                                freq /= 1.0e6;
+                            else
+                                log_error("unsupported frequency unit '%s'\n", unit.c_str());
+                            addClock(id(target), freq);
+                        } else {
+                            log_warning("    ignoring unsupported LPF command '%s %s'\n", command.c_str(),
+                                        etype.c_str());
+                        }
                     } else if (verb == "LOCATE") {
                         NPNR_ASSERT(words.at(1) == "COMP");
                         std::string cell = strip_quotes(words.at(2));
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 84fce1c7..64682fd2 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -20,6 +20,7 @@
 #include <algorithm>
 #include <boost/optional.hpp>
 #include <iterator>
+#include <queue>
 #include <unordered_set>
 #include "cells.h"
 #include "chain_utils.h"
@@ -1396,6 +1397,233 @@ class Ecp5Packer
         return a->driver.cell->type == b->driver.cell->type;
     }
 
+    struct EdgeClockInfo
+    {
+        CellInfo *buffer = nullptr;
+        NetInfo *unbuf = nullptr;
+        NetInfo *buf = nullptr;
+    };
+
+    std::map<std::pair<int, int>, EdgeClockInfo> eclks;
+
+    void make_eclk(PortInfo &usr_port, CellInfo *usr_cell, BelId usr_bel, int bank)
+    {
+        NetInfo *ecknet = usr_port.net;
+        if (ecknet == nullptr)
+            log_error("Input '%s' of cell '%s' cannot be disconnected\n", usr_port.name.c_str(ctx),
+                      usr_cell->name.c_str(ctx));
+        int found_eclk = -1, free_eclk = -1;
+        for (int i = 0; i < 2; i++) {
+            if (eclks.count(std::make_pair(bank, i))) {
+                if (eclks.at(std::make_pair(bank, i)).unbuf == ecknet) {
+                    found_eclk = i;
+                    break;
+                }
+            } else if (free_eclk == -1) {
+                free_eclk = i;
+            }
+        }
+        if (found_eclk == -1) {
+            if (free_eclk == -1) {
+                log_error("Unable to promote edge clock '%s' for bank %d. 2/2 edge clocks already used by '%s' and "
+                          "'%s'.\n",
+                          ecknet->name.c_str(ctx), bank, eclks.at(std::make_pair(bank, 0)).unbuf->name.c_str(ctx),
+                          eclks.at(std::make_pair(bank, 1)).unbuf->name.c_str(ctx));
+            } else {
+                log_info("Promoted '%s' to bank %d ECLK%d.\n", ecknet->name.c_str(ctx), bank, free_eclk);
+                auto &eclk = eclks[std::make_pair(bank, free_eclk)];
+                eclk.unbuf = ecknet;
+                IdString eckname = ctx->id(ecknet->name.str(ctx) + "$eclk" + std::to_string(bank) + "_" +
+                                           std::to_string(free_eclk));
+
+                std::unique_ptr<NetInfo> promoted_ecknet(new NetInfo);
+                promoted_ecknet->name = eckname;
+                promoted_ecknet->is_global = true; // Prevents router etc touching this special net
+                eclk.buf = promoted_ecknet.get();
+                NPNR_ASSERT(!ctx->nets.count(eckname));
+                ctx->nets[eckname] = std::move(promoted_ecknet);
+
+                // Insert TRELLIS_ECLKBUF to isolate edge clock from general routing
+                std::unique_ptr<CellInfo> eclkbuf =
+                        create_ecp5_cell(ctx, id_TRELLIS_ECLKBUF, eckname.str(ctx) + "$buffer");
+                BelId target_bel;
+                // Find the correct Bel for the ECLKBUF
+                IdString eclkname = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(free_eclk));
+                for (auto bel : ctx->getBels()) {
+                    if (ctx->getBelType(bel) != id_TRELLIS_ECLKBUF)
+                        continue;
+                    if (ctx->getWireBasename(ctx->getBelPinWire(bel, id_ECLKO)) != eclkname)
+                        continue;
+                    target_bel = bel;
+                    break;
+                }
+                NPNR_ASSERT(target_bel != BelId());
+
+                eclkbuf->attrs[ctx->id("BEL")] = ctx->getBelName(target_bel).str(ctx);
+
+                connect_port(ctx, ecknet, eclkbuf.get(), id_ECLKI);
+                connect_port(ctx, eclk.buf, eclkbuf.get(), id_ECLKO);
+                found_eclk = free_eclk;
+                eclk.buffer = eclkbuf.get();
+                new_cells.push_back(std::move(eclkbuf));
+            }
+        }
+
+        auto &eclk = eclks[std::make_pair(bank, found_eclk)];
+        disconnect_port(ctx, usr_cell, usr_port.name);
+        usr_port.net = nullptr;
+        connect_port(ctx, eclk.buf, usr_cell, usr_port.name);
+
+        // Simple ECLK router
+        WireId userWire = ctx->getBelPinWire(usr_bel, usr_port.name);
+        IdString bnke_name = ctx->id("BNK_ECLK" + std::to_string(found_eclk));
+        IdString global_name = ctx->id("G_BANK" + std::to_string(bank) + "ECLK" + std::to_string(found_eclk));
+
+        std::queue<WireId> upstream;
+        std::unordered_map<WireId, PipId> backtrace;
+        upstream.push(userWire);
+        WireId next;
+        while (true) {
+            if (upstream.empty() || upstream.size() > 30000)
+                log_error("failed to route bank %d ECLK%d to %s.%s\n", bank, found_eclk,
+                          ctx->getBelName(usr_bel).c_str(ctx), usr_port.name.c_str(ctx));
+            next = upstream.front();
+            upstream.pop();
+            if (ctx->debug)
+                log_info("    visited %s\n", ctx->getWireName(next).c_str(ctx));
+            IdString basename = ctx->getWireBasename(next);
+            if (basename == bnke_name || basename == global_name) {
+                break;
+            }
+            if (ctx->checkWireAvail(next)) {
+                for (auto pip : ctx->getPipsUphill(next)) {
+                    WireId src = ctx->getPipSrcWire(pip);
+                    backtrace[src] = pip;
+                    upstream.push(src);
+                }
+            }
+        }
+        // Set all the pips we found along the way
+        WireId cursor = next;
+        while (true) {
+            auto fnd = backtrace.find(cursor);
+            if (fnd == backtrace.end())
+                break;
+            ctx->bindPip(fnd->second, eclk.buf, STRENGTH_LOCKED);
+            cursor = ctx->getPipDstWire(fnd->second);
+        }
+    }
+
+    void tie_zero(CellInfo *ci, IdString port)
+    {
+
+        if (!ci->ports.count(port)) {
+            ci->ports[port].name = port;
+            ci->ports[port].type = PORT_IN;
+        }
+
+        std::unique_ptr<CellInfo> zero_cell{new CellInfo};
+        std::unique_ptr<NetInfo> zero_net{new NetInfo};
+        IdString name = ctx->id(ci->name.str(ctx) + "$zero$" + port.str(ctx));
+        zero_cell->type = ctx->id("GND");
+        zero_cell->name = name;
+        zero_net->name = name;
+        zero_cell->ports[ctx->id("GND")].type = PORT_OUT;
+        connect_port(ctx, zero_net.get(), zero_cell.get(), ctx->id("GND"));
+        connect_port(ctx, zero_net.get(), ci, port);
+        ctx->nets[name] = std::move(zero_net);
+        new_cells.push_back(std::move(zero_cell));
+    }
+
+    std::unordered_map<IdString, std::pair<bool, int>> dqsbuf_dqsg;
+    // Pack DQSBUFs
+    void pack_dqsbuf()
+    {
+        for (auto cell : sorted(ctx->cells)) {
+            CellInfo *ci = cell.second;
+            if (ci->type == id_DQSBUFM) {
+                CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("DQSI")).net, is_trellis_io, id_O);
+                if (pio == nullptr || ci->ports.at(ctx->id("DQSI")).net->users.size() > 1)
+                    log_error("DQSBUFM '%s' DQSI input must be connected only to a top level input\n",
+                              ci->name.c_str(ctx));
+                if (!pio->attrs.count(ctx->id("BEL")))
+                    log_error("DQSBUFM can only be used with a pin-constrained PIO connected to its DQSI input"
+                              "(while processing '%s').\n",
+                              ci->name.c_str(ctx));
+                BelId pio_bel = ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL"))));
+                NPNR_ASSERT(pio_bel != BelId());
+                Loc pio_loc = ctx->getBelLocation(pio_bel);
+                if (pio_loc.z != 0)
+                    log_error("PIO '%s' does not appear to be a DQS site (expecting an 'A' pin).\n",
+                              ctx->getBelName(pio_bel).c_str(ctx));
+                pio_loc.z = 8;
+                BelId dqsbuf = ctx->getBelByLocation(pio_loc);
+                if (dqsbuf == BelId() || ctx->getBelType(dqsbuf) != id_DQSBUFM)
+                    log_error("PIO '%s' does not appear to be a DQS site (didn't find a DQSBUFM).\n",
+                              ctx->getBelName(pio_bel).c_str(ctx));
+                ci->attrs[ctx->id("BEL")] = ctx->getBelName(dqsbuf).str(ctx);
+                bool got_dqsg = ctx->getPIODQSGroup(pio_bel, dqsbuf_dqsg[ci->name].first, dqsbuf_dqsg[ci->name].second);
+                NPNR_ASSERT(got_dqsg);
+                log_info("Constrained DQSBUFM '%s' to %cDQS%d\n", ci->name.c_str(ctx),
+                         dqsbuf_dqsg[ci->name].first ? 'R' : 'L', dqsbuf_dqsg[ci->name].second);
+
+                // Set all special ports, if used as 'globals' that the router won't touch
+                for (auto port : {id_DQSR90, id_RDPNTR0, id_RDPNTR1, id_RDPNTR2, id_WRPNTR0, id_WRPNTR1, id_WRPNTR2,
+                                  id_DQSW270, id_DQSW}) {
+                    if (!ci->ports.count(port))
+                        continue;
+                    NetInfo *pn = ci->ports.at(port).net;
+                    if (pn == nullptr)
+                        continue;
+                    for (auto &usr : pn->users) {
+                        if (usr.port != port ||
+                            (usr.cell->type != ctx->id("ODDRX2DQA") && usr.cell->type != ctx->id("ODDRX2DQSB") &&
+                             usr.cell->type != ctx->id("TSHX2DQSA") && usr.cell->type != ctx->id("IDDRX2DQA") &&
+                             usr.cell->type != ctx->id("TSHX2DQA") && usr.cell->type != id_IOLOGIC))
+                            log_error("Port '%s' of DQSBUFM '%s' cannot drive port '%s' of cell '%s'.\n",
+                                      port.c_str(ctx), ci->name.c_str(ctx), usr.port.c_str(ctx),
+                                      usr.cell->name.c_str(ctx));
+                    }
+                    pn->is_global = true;
+                }
+
+                for (auto zport :
+                     {id_RDMOVE, id_RDDIRECTION, id_WRMOVE, id_WRDIRECTION, id_READ0, id_READ1, id_READCLKSEL0,
+                      id_READCLKSEL1, id_READCLKSEL2, id_DYNDELAY0, id_DYNDELAY1, id_DYNDELAY2, id_DYNDELAY3,
+                      id_DYNDELAY4, id_DYNDELAY5, id_DYNDELAY6, id_DYNDELAY7}) {
+                    if (net_or_nullptr(ci, zport) == nullptr)
+                        tie_zero(ci, zport);
+                }
+            }
+        }
+    }
+
+    int lookup_delay(const std::string &del_mode)
+    {
+        if (del_mode == "USER_DEFINED")
+            return 0;
+        else if (del_mode == "DQS_ALIGNED_X2")
+            return 6;
+        else if (del_mode == "DQS_CMD_CLK")
+            return 9;
+        else if (del_mode == "ECLK_ALIGNED")
+            return 21;
+        else if (del_mode == "ECLK_CENTERED")
+            return 11;
+        else if (del_mode == "ECLKBRIDGE_ALIGNED")
+            return 39;
+        else if (del_mode == "ECLKBRIDGE_CENTERED")
+            return 29;
+        else if (del_mode == "SCLK_ALIGNED")
+            return 50;
+        else if (del_mode == "SCLK_CENTERED")
+            return 39;
+        else if (del_mode == "SCLK_ZEROHOLD")
+            return 59;
+        else
+            log_error("Unsupported DEL_MODE '%s'\n", del_mode.c_str());
+    }
+
     // Pack IOLOGIC
     void pack_iologic()
     {
@@ -1421,6 +1649,24 @@ class Ecp5Packer
                 disconnect_port(ctx, prim, port);
         };
 
+        auto set_iologic_eclk = [&](CellInfo *iol, CellInfo *prim, IdString port) {
+            NetInfo *eclk = nullptr;
+            if (prim->ports.count(port))
+                eclk = prim->ports[port].net;
+            if (eclk == nullptr)
+                log_error("%s '%s' cannot have disconnected ECLK", prim->type.c_str(ctx), prim->name.c_str(ctx));
+
+            if (iol->ports[id_ECLK].net != nullptr) {
+                if (iol->ports[id_ECLK].net != eclk)
+                    log_error("IOLOGIC '%s' has conflicting ECLKs '%s' and '%s'\n", iol->name.c_str(ctx),
+                              iol->ports[id_ECLK].net->name.c_str(ctx), eclk->name.c_str(ctx));
+            } else {
+                connect_port(ctx, eclk, iol, id_ECLK);
+            }
+            if (prim->ports.count(port))
+                disconnect_port(ctx, prim, port);
+        };
+
         auto set_iologic_lsr = [&](CellInfo *iol, CellInfo *prim, IdString port, bool input) {
             NetInfo *lsr = nullptr;
             if (prim->ports.count(port))
@@ -1433,7 +1679,7 @@ class Ecp5Packer
                     if (iol->ports[id_LSR].net != lsr)
                         log_error("IOLOGIC '%s' has conflicting LSR signals '%s' and '%s'\n", iol->name.c_str(ctx),
                                   iol->ports[id_LSR].net->name.c_str(ctx), lsr->name.c_str(ctx));
-                } else {
+                } else if (iol->ports[id_LSR].net == nullptr) {
                     connect_port(ctx, lsr, iol, id_LSR);
                 }
             }
@@ -1443,19 +1689,27 @@ class Ecp5Packer
 
         auto set_iologic_mode = [&](CellInfo *iol, std::string mode) {
             auto &curr_mode = iol->params[ctx->id("MODE")];
-            if (curr_mode != "NONE" && curr_mode != mode)
+            if (curr_mode != "NONE" && curr_mode != "IREG_OREG" && curr_mode != mode)
                 log_error("IOLOGIC '%s' has conflicting modes '%s' and '%s'\n", iol->name.c_str(ctx), curr_mode.c_str(),
                           mode.c_str());
+            if (iol->type == id_SIOLOGIC && mode != "IREG_OREG" && mode != "IDDRX1_ODDRX1" && mode != "NONE")
+                log_error("IOLOGIC '%s' is set to mode '%s', but this is only supported for left and right IO\n",
+                          iol->name.c_str(ctx), mode.c_str());
             curr_mode = mode;
         };
 
-        auto create_pio_iologic = [&](CellInfo *pio, CellInfo *curr) {
+        auto get_pio_bel = [&](CellInfo *pio, CellInfo *curr) {
             if (!pio->attrs.count(ctx->id("BEL")))
                 log_error("IOLOGIC functionality (DDR, DELAY, DQS, etc) can only be used with pin-constrained PIO "
                           "(while processing '%s').\n",
                           curr->name.c_str(ctx));
             BelId bel = ctx->getBelByName(ctx->id(pio->attrs.at(ctx->id("BEL"))));
             NPNR_ASSERT(bel != BelId());
+            return bel;
+        };
+
+        auto create_pio_iologic = [&](CellInfo *pio, CellInfo *curr) {
+            BelId bel = get_pio_bel(pio, curr);
             log_info("IOLOGIC component %s connected to PIO Bel %s\n", curr->name.c_str(ctx),
                      ctx->getBelName(bel).c_str(ctx));
             Loc loc = ctx->getBelLocation(bel);
@@ -1474,6 +1728,122 @@ class Ecp5Packer
             return iol_ptr;
         };
 
+        auto process_dqs_port = [&](CellInfo *prim, CellInfo *pio, CellInfo *iol, IdString port) {
+            NetInfo *sig = nullptr;
+            if (prim->ports.count(port))
+                sig = prim->ports[port].net;
+            if (sig == nullptr || sig->driver.cell == nullptr)
+                log_error("Port %s of cell '%s' cannot be disconnected, it must be driven by a DQSBUFM\n",
+                          port.c_str(ctx), prim->name.c_str(ctx));
+            if (iol->ports.at(port).net != nullptr) {
+                if (iol->ports.at(port).net != sig) {
+                    log_error("IOLOGIC '%s' has conflicting %s signals '%s' and '%s'\n", iol->name.c_str(ctx),
+                              port.c_str(ctx), iol->ports[port].net->name.c_str(ctx), sig->name.c_str(ctx));
+                }
+                disconnect_port(ctx, prim, port);
+            } else {
+                bool dqsr;
+                int dqsgroup;
+                bool has_dqs = ctx->getPIODQSGroup(get_pio_bel(pio, prim), dqsr, dqsgroup);
+                if (!has_dqs)
+                    log_error("Primitive '%s' cannot be connected to top level port '%s' as the associated pin is not "
+                              "in any DQS group",
+                              prim->name.c_str(ctx), pio->name.c_str(ctx));
+                if (sig->driver.cell->type != id_DQSBUFM || sig->driver.port != port)
+                    log_error("Port %s of cell '%s' must be driven by port %s of a DQSBUFM", port.c_str(ctx),
+                              prim->name.c_str(ctx), port.c_str(ctx));
+                auto &driver_group = dqsbuf_dqsg.at(sig->driver.cell->name);
+                if (driver_group.first != dqsr || driver_group.second != dqsgroup)
+                    log_error("DQS group mismatch, port %s of '%s' in group %cDQ%d is driven by DQSBUFM '%s' in group "
+                              "%cDQ%d\n",
+                              port.c_str(ctx), prim->name.c_str(ctx), dqsr ? 'R' : 'L', dqsgroup,
+                              sig->driver.cell->name.c_str(ctx), driver_group.first ? 'R' : 'L', driver_group.second);
+                replace_port(prim, port, iol, port);
+            }
+        };
+
+        for (auto cell : sorted(ctx->cells)) {
+            CellInfo *ci = cell.second;
+            if (ci->type == ctx->id("DELAYF") || ci->type == ctx->id("DELAYG")) {
+                CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(ctx->id("A")).net, is_trellis_io, id_O);
+                CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(ctx->id("Z")).net, is_trellis_io, id_I, true);
+                CellInfo *iol = nullptr;
+                if (i_pio != nullptr && ci->ports.at(ctx->id("A")).net->users.size() == 1) {
+                    iol = create_pio_iologic(i_pio, ci);
+                    set_iologic_mode(iol, "IREG_OREG");
+                    bool drives_iologic = false;
+                    for (auto user : ci->ports.at(ctx->id("Z")).net->users)
+                        if (is_iologic_input_cell(ctx, user.cell) && user.port == ctx->id("D"))
+                            drives_iologic = true;
+                    if (drives_iologic) {
+                        // Reconnect to PIO which the packer expects later on
+                        NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
+                        disconnect_port(ctx, i_pio, id_O);
+                        i_pio->ports.at(id_O).net = nullptr;
+                        disconnect_port(ctx, ci, id_A);
+                        ci->ports.at(id_A).net = nullptr;
+                        disconnect_port(ctx, ci, id_Z);
+                        ci->ports.at(id_Z).net = nullptr;
+                        connect_port(ctx, dly_net, i_pio, id_O);
+                        connect_port(ctx, input_net, iol, id_INDD);
+                        connect_port(ctx, input_net, iol, id_DI);
+                    } else {
+                        replace_port(ci, id_A, iol, id_PADDI);
+                        replace_port(ci, id_Z, iol, id_INDD);
+                    }
+                    packed_cells.insert(cell.first);
+                } else if (o_pio != nullptr) {
+                    iol = create_pio_iologic(o_pio, ci);
+                    iol->params[ctx->id("DELAY.OUTDEL")] = "ENABLED";
+                    bool driven_by_iol = false;
+                    NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
+                    if (input_net->driver.cell != nullptr && is_iologic_output_cell(ctx, input_net->driver.cell) &&
+                        input_net->driver.port == ctx->id("Q"))
+                        driven_by_iol = true;
+                    if (driven_by_iol) {
+                        disconnect_port(ctx, o_pio, id_I);
+                        o_pio->ports.at(id_I).net = nullptr;
+                        disconnect_port(ctx, ci, id_A);
+                        ci->ports.at(id_A).net = nullptr;
+                        disconnect_port(ctx, ci, id_Z);
+                        ci->ports.at(id_Z).net = nullptr;
+                        connect_port(ctx, input_net, o_pio, id_I);
+                        ctx->nets.erase(dly_net->name);
+                    } else {
+                        replace_port(ci, ctx->id("A"), iol, id_TXDATA0);
+                        replace_port(ci, ctx->id("Z"), iol, id_IOLDO);
+                        if (!o_pio->ports.count(id_IOLDO)) {
+                            o_pio->ports[id_IOLDO].name = id_IOLDO;
+                            o_pio->ports[id_IOLDO].type = PORT_IN;
+                        }
+                        replace_port(o_pio, id_I, o_pio, id_IOLDO);
+                    }
+                    packed_cells.insert(cell.first);
+                } else {
+                    log_error("%s '%s' must be connected directly to top level input or output\n", ci->type.c_str(ctx),
+                              ci->name.c_str(ctx));
+                }
+                iol->params[ctx->id("DELAY.DEL_VALUE")] =
+                        std::to_string(lookup_delay(str_or_default(ci->params, ctx->id("DEL_MODE"), "USER_DEFINED")));
+                if (ci->params.count(ctx->id("DEL_VALUE")) && ci->params.at(ctx->id("DEL_VALUE")) != "DELAY0")
+                    iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(ctx->id("DEL_VALUE"));
+                if (ci->ports.count(id_LOADN))
+                    replace_port(ci, id_LOADN, iol, id_LOADN);
+                else
+                    tie_zero(ci, id_LOADN);
+                if (ci->ports.count(id_MOVE))
+                    replace_port(ci, id_MOVE, iol, id_MOVE);
+                else
+                    tie_zero(ci, id_MOVE);
+                if (ci->ports.count(id_DIRECTION))
+                    replace_port(ci, id_DIRECTION, iol, id_DIRECTION);
+                else
+                    tie_zero(ci, id_DIRECTION);
+                if (ci->ports.count(id_CFLAG))
+                    replace_port(ci, id_CFLAG, iol, id_CFLAG);
+            }
+        }
+
         for (auto cell : sorted(ctx->cells)) {
             CellInfo *ci = cell.second;
             if (ci->type == ctx->id("IDDRX1F")) {
@@ -1518,15 +1888,427 @@ class Ecp5Packer
                 replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
                 iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
                 packed_cells.insert(cell.first);
+            } else if (ci->type == ctx->id("ODDRX2F")) {
+                CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+                if (pio == nullptr)
+                    log_error("ODDRX2F '%s' Q output must be connected only to a top level output\n",
+                              ci->name.c_str(ctx));
+                CellInfo *iol;
+                if (pio_iologic.count(pio->name))
+                    iol = pio_iologic.at(pio->name);
+                else
+                    iol = create_pio_iologic(pio, ci);
+                set_iologic_mode(iol, "ODDRXN");
+                replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+                if (!pio->ports.count(id_IOLDO)) {
+                    pio->ports[id_IOLDO].name = id_IOLDO;
+                    pio->ports[id_IOLDO].type = PORT_IN;
+                }
+                replace_port(pio, id_I, pio, id_IOLDO);
+                set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+                set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+                set_iologic_eclk(iol, ci, id_ECLK);
+                set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+                replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
+                replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
+                replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
+                replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
+                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                iol->params[ctx->id("ODDRXN.MODE")] = "ODDRX2";
+                pio->params[ctx->id("DATAMUX_ODDR")] = "IOLDO";
+                packed_cells.insert(cell.first);
+            } else if (ci->type == ctx->id("IDDRX2F")) {
+                CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
+                if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+                    log_error("IDDRX2F '%s' D input must be connected only to a top level input\n",
+                              ci->name.c_str(ctx));
+                CellInfo *iol;
+                if (pio_iologic.count(pio->name))
+                    iol = pio_iologic.at(pio->name);
+                else
+                    iol = create_pio_iologic(pio, ci);
+                set_iologic_mode(iol, "IDDRXN");
+                replace_port(ci, ctx->id("D"), iol, id_PADDI);
+                set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+                set_iologic_eclk(iol, ci, id_ECLK);
+                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+                replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
+                replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
+                replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
+                replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
+                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                iol->params[ctx->id("IDDRXN.MODE")] = "IDDRX2";
+                packed_cells.insert(cell.first);
+            } else if (ci->type == ctx->id("OSHX2A")) {
+                CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+                if (pio == nullptr)
+                    log_error("OSHX2A '%s' Q output must be connected only to a top level output\n",
+                              ci->name.c_str(ctx));
+                CellInfo *iol;
+                if (pio_iologic.count(pio->name))
+                    iol = pio_iologic.at(pio->name);
+                else
+                    iol = create_pio_iologic(pio, ci);
+                set_iologic_mode(iol, "MIDDRX_MODDRX");
+                replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+                if (!pio->ports.count(id_IOLDO)) {
+                    pio->ports[id_IOLDO].name = id_IOLDO;
+                    pio->ports[id_IOLDO].type = PORT_IN;
+                }
+                replace_port(pio, id_I, pio, id_IOLDO);
+                set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+                set_iologic_eclk(iol, ci, id_ECLK);
+                set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+                replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
+                replace_port(ci, ctx->id("D1"), iol, id_TXDATA2);
+                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                iol->params[ctx->id("MODDRX.MODE")] = "MOSHX2";
+                pio->params[ctx->id("DATAMUX_MDDR")] = "IOLDO";
+                packed_cells.insert(cell.first);
+            } else if (ci->type == ctx->id("ODDRX2DQA") || ci->type == ctx->id("ODDRX2DQSB")) {
+                CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+                if (pio == nullptr)
+                    log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
+                              ci->name.c_str(ctx));
+                CellInfo *iol;
+                if (pio_iologic.count(pio->name))
+                    iol = pio_iologic.at(pio->name);
+                else
+                    iol = create_pio_iologic(pio, ci);
+                set_iologic_mode(iol, "MIDDRX_MODDRX");
+                replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+                if (!pio->ports.count(id_IOLDO)) {
+                    pio->ports[id_IOLDO].name = id_IOLDO;
+                    pio->ports[id_IOLDO].type = PORT_IN;
+                }
+                replace_port(pio, id_I, pio, id_IOLDO);
+                set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+                set_iologic_eclk(iol, ci, id_ECLK);
+                set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+                replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
+                replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
+                replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
+                replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
+                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                iol->params[ctx->id("MODDRX.MODE")] = "MODDRX2";
+                iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = ci->type == ctx->id("ODDRX2DQSB") ? "DQSW" : "DQSW270";
+                process_dqs_port(ci, pio, iol, ci->type == ctx->id("ODDRX2DQSB") ? id_DQSW : id_DQSW270);
+                pio->params[ctx->id("DATAMUX_MDDR")] = "IOLDO";
+                packed_cells.insert(cell.first);
+            } else if (ci->type == ctx->id("IDDRX2DQA")) {
+                CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
+                if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+                    log_error("IDDRX2DQA '%s' D input must be connected only to a top level input\n",
+                              ci->name.c_str(ctx));
+                CellInfo *iol;
+                if (pio_iologic.count(pio->name))
+                    iol = pio_iologic.at(pio->name);
+                else
+                    iol = create_pio_iologic(pio, ci);
+                set_iologic_mode(iol, "MIDDRX_MODDRX");
+                replace_port(ci, ctx->id("D"), iol, id_PADDI);
+                set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+                set_iologic_eclk(iol, ci, id_ECLK);
+                set_iologic_lsr(iol, ci, ctx->id("RST"), true);
+                replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
+                replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
+                replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
+                replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
+                replace_port(ci, ctx->id("QWL"), iol, id_INFF);
+                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                iol->params[ctx->id("MIDDRX.MODE")] = "MIDDRX2";
+                process_dqs_port(ci, pio, iol, id_DQSR90);
+                process_dqs_port(ci, pio, iol, id_RDPNTR2);
+                process_dqs_port(ci, pio, iol, id_RDPNTR1);
+                process_dqs_port(ci, pio, iol, id_RDPNTR0);
+                process_dqs_port(ci, pio, iol, id_WRPNTR2);
+                process_dqs_port(ci, pio, iol, id_WRPNTR1);
+                process_dqs_port(ci, pio, iol, id_WRPNTR0);
+                packed_cells.insert(cell.first);
+            } else if (ci->type == ctx->id("TSHX2DQA") || ci->type == ctx->id("TSHX2DQSA")) {
+                CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
+                if (pio == nullptr)
+                    log_error("%s '%s' Q output must be connected only to a top level tristate\n", ci->type.c_str(ctx),
+                              ci->name.c_str(ctx));
+                CellInfo *iol;
+                if (pio_iologic.count(pio->name))
+                    iol = pio_iologic.at(pio->name);
+                else
+                    iol = create_pio_iologic(pio, ci);
+                set_iologic_mode(iol, "MIDDRX_MODDRX");
+                replace_port(ci, ctx->id("Q"), iol, id_IOLTO);
+                if (!pio->ports.count(id_IOLTO)) {
+                    pio->ports[id_IOLTO].name = id_IOLTO;
+                    pio->ports[id_IOLTO].type = PORT_IN;
+                }
+                replace_port(pio, id_T, pio, id_IOLTO);
+                set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+                set_iologic_eclk(iol, ci, id_ECLK);
+                set_iologic_lsr(iol, ci, ctx->id("RST"), false);
+                replace_port(ci, ctx->id("T0"), iol, id_TSDATA0);
+                replace_port(ci, ctx->id("T1"), iol, id_TSDATA1);
+                process_dqs_port(ci, pio, iol, ci->type == ctx->id("TSHX2DQSA") ? id_DQSW : id_DQSW270);
+                iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+                iol->params[ctx->id("MTDDRX.MODE")] = "MTSHX2";
+                iol->params[ctx->id("MTDDRX.REGSET")] = "SET";
+                iol->params[ctx->id("MTDDRX.DQSW_INVERT")] = ci->type == ctx->id("TSHX2DQSA") ? "ENABLED" : "DISABLED";
+                iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] = ci->type == ctx->id("TSHX2DQSA") ? "DQSW" : "DQSW270";
+                iol->params[ctx->id("IOLTOMUX")] = "TDDR";
+                packed_cells.insert(cell.first);
+            }
+        }
+        flush_cells();
+        // Promote/route edge clocks
+        for (auto cell : sorted(ctx->cells)) {
+            CellInfo *ci = cell.second;
+            if (ci->type == id_IOLOGIC || ci->type == id_DQSBUFM) {
+                if (!ci->ports.count(id_ECLK) || ci->ports.at(id_ECLK).net == nullptr)
+                    continue;
+                BelId bel = ctx->getBelByName(ctx->id(str_or_default(ci->attrs, ctx->id("BEL"))));
+                NPNR_ASSERT(bel != BelId());
+                Loc pioLoc = ctx->getBelLocation(bel);
+                if (ci->type == id_DQSBUFM)
+                    pioLoc.z -= 8;
+                else
+                    pioLoc.z -= 4;
+                BelId pioBel = ctx->getBelByLocation(pioLoc);
+                NPNR_ASSERT(pioBel != BelId());
+                int bank = ctx->getPioBelBank(pioBel);
+                make_eclk(ci->ports.at(id_ECLK), ci, bel, bank);
             }
         }
         flush_cells();
+        // Constrain ECLK-related cells
+        for (auto cell : sorted(ctx->cells)) {
+            CellInfo *ci = cell.second;
+            if (ci->type == id_CLKDIVF) {
+                const NetInfo *clki = net_or_nullptr(ci, id_CLKI);
+                for (auto &eclk : eclks) {
+                    if (eclk.second.unbuf == clki) {
+                        for (auto bel : ctx->getBels()) {
+                            if (ctx->getBelType(bel) != id_CLKDIVF)
+                                continue;
+                            Loc loc = ctx->getBelLocation(bel);
+                            // CLKDIVF for bank 6/7 on the left; for bank 2/3 on the right
+                            if (loc.x < 10 && eclk.first.first != 6 && eclk.first.first != 7)
+                                continue;
+                            // z-index of CLKDIVF must match index of ECLK
+                            if (loc.z != eclk.first.second)
+                                continue;
+                            ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+                            make_eclk(ci->ports.at(id_CLKI), ci, bel, eclk.first.first);
+                            goto clkdiv_done;
+                        }
+                    }
+                }
+            clkdiv_done:
+                continue;
+            } else if (ci->type == id_ECLKSYNCB) {
+                const NetInfo *eclko = net_or_nullptr(ci, id_ECLKO);
+                if (eclko == nullptr)
+                    log_error("ECLKSYNCB '%s' has disconnected port ECLKO\n", ci->name.c_str(ctx));
+                for (auto user : eclko->users) {
+                    if (user.cell->type == id_TRELLIS_ECLKBUF) {
+                        Loc eckbuf_loc =
+                                ctx->getBelLocation(ctx->getBelByName(ctx->id(user.cell->attrs.at(ctx->id("BEL")))));
+                        for (auto bel : ctx->getBels()) {
+                            if (ctx->getBelType(bel) != id_ECLKSYNCB)
+                                continue;
+                            Loc loc = ctx->getBelLocation(bel);
+                            if (loc.x == eckbuf_loc.x && loc.y == eckbuf_loc.y && loc.z == eckbuf_loc.z - 2) {
+                                ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+                                goto eclksync_done;
+                            }
+                        }
+                    }
+                }
+            eclksync_done:
+                continue;
+            } else if (ci->type == ctx->id("DDRDLLA")) {
+                ci->type = id_DDRDLL; // transform from Verilog to Bel name
+                const NetInfo *clk = net_or_nullptr(ci, id_CLK);
+                if (clk == nullptr)
+                    log_error("DDRDLLA '%s' has disconnected port CLK\n", ci->name.c_str(ctx));
+                for (auto &eclk : eclks) {
+                    if (eclk.second.unbuf == clk) {
+                        for (auto bel : ctx->getBels()) {
+                            if (ctx->getBelType(bel) != id_DDRDLL)
+                                continue;
+                            Loc loc = ctx->getBelLocation(bel);
+                            int ddrdll_bank = -1;
+                            if (loc.x < 15 && loc.y < 15)
+                                ddrdll_bank = 7;
+                            else if (loc.x < 15 && loc.y > 15)
+                                ddrdll_bank = 6;
+                            else if (loc.x > 15 && loc.y < 15)
+                                ddrdll_bank = 2;
+                            else if (loc.x > 15 && loc.y > 15)
+                                ddrdll_bank = 3;
+                            if (eclk.first.first != ddrdll_bank)
+                                continue;
+                            ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+                            make_eclk(ci->ports.at(id_CLK), ci, bel, eclk.first.first);
+                            goto ddrdll_done;
+                        }
+                    }
+                }
+            ddrdll_done:
+                continue;
+            }
+        }
+
+        flush_cells();
     };
 
+    void generate_constraints()
+    {
+        log_info("Generating derived timing constraints...\n");
+        auto MHz = [&](delay_t a) { return 1000.0 / ctx->getDelayNS(a); };
+
+        auto equals_epsilon = [](delay_t a, delay_t b) { return (std::abs(a - b) / std::max(double(b), 1.0)) < 1e-3; };
+
+        std::unordered_set<IdString> user_constrained, changed_nets;
+        for (auto &net : ctx->nets) {
+            if (net.second->clkconstr != nullptr)
+                user_constrained.insert(net.first);
+            changed_nets.insert(net.first);
+        }
+        auto get_period = [&](CellInfo *ci, IdString port, delay_t &period) {
+            if (!ci->ports.count(port))
+                return false;
+            NetInfo *from = ci->ports.at(port).net;
+            if (from == nullptr || from->clkconstr == nullptr)
+                return false;
+            period = from->clkconstr->period.min_delay;
+            return true;
+        };
+
+        auto set_period = [&](CellInfo *ci, IdString port, delay_t period) {
+            if (!ci->ports.count(port))
+                return;
+            NetInfo *to = ci->ports.at(port).net;
+            if (to == nullptr)
+                return;
+            if (to->clkconstr != nullptr) {
+                if (!equals_epsilon(to->clkconstr->period.min_delay, period) && user_constrained.count(to->name))
+                    log_warning(
+                            "    Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
+                            "%.1f MHz.\n",
+                            MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx), MHz(period));
+                return;
+            }
+            to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+            to->clkconstr->low.min_delay = period / 2;
+            to->clkconstr->low.max_delay = period / 2;
+            to->clkconstr->high.min_delay = period / 2;
+            to->clkconstr->high.max_delay = period / 2;
+            to->clkconstr->period.min_delay = period;
+            to->clkconstr->period.max_delay = period;
+            log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
+                     to->name.c_str(ctx));
+            changed_nets.insert(to->name);
+        };
+
+        auto copy_constraint = [&](CellInfo *ci, IdString fromPort, IdString toPort, double ratio = 1.0) {
+            if (!ci->ports.count(fromPort) || !ci->ports.count(toPort))
+                return;
+            NetInfo *from = ci->ports.at(fromPort).net, *to = ci->ports.at(toPort).net;
+            if (from == nullptr || from->clkconstr == nullptr || to == nullptr)
+                return;
+            if (to->clkconstr != nullptr) {
+                if (!equals_epsilon(to->clkconstr->period.min_delay,
+                                    delay_t(from->clkconstr->period.min_delay / ratio)) &&
+                    user_constrained.count(to->name))
+                    log_warning(
+                            "    Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
+                            "%.1f MHz.\n",
+                            MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx),
+                            MHz(delay_t(from->clkconstr->period.min_delay / ratio)));
+                return;
+            }
+            to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
+            to->clkconstr->low = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio);
+            to->clkconstr->high = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio);
+            to->clkconstr->period = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio);
+            log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
+                     to->name.c_str(ctx));
+            changed_nets.insert(to->name);
+        };
+
+        // Run in a loop while constraints are changing to deal with dependencies
+        // Iteration limit avoids hanging in crazy loopback situation (self-fed PLLs or dividers, etc)
+        int iter = 0;
+        const int itermax = 5000;
+        while (!changed_nets.empty() && iter < itermax) {
+            ++iter;
+            std::unordered_set<IdString> changed_cells;
+            for (auto net : changed_nets)
+                for (auto &user : ctx->nets.at(net)->users)
+                    if (user.port == id_CLKI || user.port == id_ECLKI)
+                        changed_cells.insert(user.cell->name);
+            changed_nets.clear();
+            for (auto cell : sorted(changed_cells)) {
+                CellInfo *ci = ctx->cells.at(cell).get();
+                if (ci->type == id_CLKDIVF) {
+                    std::string div = str_or_default(ci->params, ctx->id("DIV"), "2.0");
+                    double ratio;
+                    if (div == "2.0")
+                        ratio = 1 / 2.0;
+                    else if (div == "3.5")
+                        ratio = 1 / 3.5;
+                    else
+                        log_error("Unsupported divider ratio '%s' on CLKDIVF '%s'\n", div.c_str(), ci->name.c_str(ctx));
+                    copy_constraint(ci, id_CLKI, id_CDIVX, ratio);
+                } else if (ci->type == id_ECLKSYNCB || ci->type == id_TRELLIS_ECLKBUF) {
+                    copy_constraint(ci, id_ECLKI, id_ECLKO, 1);
+                } else if (ci->type == id_EHXPLLL) {
+                    delay_t period_in;
+                    if (!get_period(ci, id_CLKI, period_in))
+                        continue;
+                    log_info("    Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
+                             MHz(period_in));
+                    double period_in_div = period_in * int_or_default(ci->params, ctx->id("CLKI_DIV"), 1);
+                    std::string path = str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP");
+                    int feedback_div = int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1);
+                    if (path == "CLKOP" || path == "INT_OP")
+                        feedback_div *= int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1);
+                    else if (path == "CLKOS" || path == "INT_OS")
+                        feedback_div *= int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1);
+                    else if (path == "CLKOS2" || path == "INT_OS2")
+                        feedback_div *= int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1);
+                    else if (path == "CLKOS3" || path == "INT_OS3")
+                        feedback_div *= int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1);
+                    else {
+                        log_info("     Unable to determine output frequencies for PLL '%s' with FEEDBK_PATH=%s\n",
+                                 ci->name.c_str(ctx), path.c_str());
+                        continue;
+                    }
+                    double vco_period = period_in_div / feedback_div;
+                    double vco_freq = MHz(vco_period);
+                    if (vco_freq < 400 || vco_freq > 800)
+                        log_info("    Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
+                                 "800MHz]\n",
+                                 vco_freq, ci->name.c_str(ctx));
+                    set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1));
+                    set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1));
+                    set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1));
+                    set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1));
+                } else if (ci->type == id_OSCG) {
+                    int div = int_or_default(ci->params, ctx->id("DIV"), 128);
+                    set_period(ci, id_OSC, delay_t((1.0e6 / (2.0 * 155)) * div));
+                }
+            }
+        }
+    }
+
   public:
     void pack()
     {
         pack_io();
+        pack_dqsbuf();
         pack_iologic();
         pack_ebr();
         pack_dsps();
@@ -1541,6 +2323,7 @@ class Ecp5Packer
         pack_lut_pairs();
         pack_remaining_luts();
         pack_remaining_ffs();
+        generate_constraints();
         promote_ecp5_globals(ctx);
         ctx->check();
     }
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index cdd3bd06..6acc32c5 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -119,9 +119,20 @@ def process_pio_db(ddrg, device):
                 pinfunc = metaitem["function"]
             else:
                 pinfunc = None
+            dqs = -1
+            if "dqs" in metaitem:
+                tdqs = metaitem["dqs"]
+                if tdqs[0] == "L":
+                    dqs = 0
+                elif tdqs[0] == "R":
+                    dqs = 2048
+                suffix_size = 0
+                while tdqs[-(suffix_size+1)].isdigit():
+                    suffix_size += 1
+                dqs |= int(tdqs[-suffix_size:])
             bel_idx = get_bel_index(ddrg, loc, pio)
             if bel_idx is not None:
-                pindata.append((loc, bel_idx, bank, pinfunc))
+                pindata.append((loc, bel_idx, bank, pinfunc, dqs))
 
 global_data = {}
 quadrants = ["UL", "UR", "LL", "LR"]
@@ -360,7 +371,7 @@ def write_database(dev_name, chip, ddrg, endianness):
 
     bba.l("pio_info", "PIOInfoPOD")
     for pin in pindata:
-        loc, bel_idx, bank, func = pin
+        loc, bel_idx, bank, func, dqs = pin
         write_loc(loc, "abs_loc")
         bba.u32(bel_idx, "bel_index")
         if func is not None:
@@ -368,7 +379,7 @@ def write_database(dev_name, chip, ddrg, endianness):
         else:
             bba.r(None, "function_name")
         bba.u16(bank, "bank")
-        bba.u16(0, "padding")
+        bba.u16(dqs, "dqsgroup")
 
     bba.l("tiletype_names", "RelPtr<char>")
     for tt, idx in sorted(tiletype_names.items(), key=lambda x: x[1]):