Replace DelayInfo with DelayPair/DelayQuad

This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.

This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.

While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.

Signed-off-by: gatecat <gatecat@ds0.me>

4 files changed, 48 insertions, 86 deletions

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index cf1745ff..8b5962d2 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -721,7 +721,7 @@ DecalXY Arch::getGroupDecal(GroupId group) const
 
 // -----------------------------------------------------------------------
 
-bool Arch::get_delay_from_tmg_db(IdString tctype, IdString from, IdString to, DelayInfo &delay) const
+bool Arch::get_delay_from_tmg_db(IdString tctype, IdString from, IdString to, DelayQuad &delay) const
 {
     auto fnd_dk = celldelay_cache.find({tctype, from, to});
     if (fnd_dk != celldelay_cache.end()) {
@@ -732,21 +732,20 @@ bool Arch::get_delay_from_tmg_db(IdString tctype, IdString from, IdString to, De
         if (tc.cell_type == tctype.index) {
             for (auto &dly : tc.prop_delays) {
                 if (dly.from_port == from.index && dly.to_port == to.index) {
-                    delay.max_delay = dly.max_delay;
-                    delay.min_delay = dly.min_delay;
+                    delay = DelayQuad(dly.min_delay, dly.max_delay);
                     celldelay_cache[{tctype, from, to}] = std::make_pair(true, delay);
                     return true;
                 }
             }
-            celldelay_cache[{tctype, from, to}] = std::make_pair(false, DelayInfo());
+            celldelay_cache[{tctype, from, to}] = std::make_pair(false, DelayQuad());
             return false;
         }
     }
     NPNR_ASSERT_FALSE("failed to find timing cell in db");
 }
 
-void Arch::get_setuphold_from_tmg_db(IdString tctype, IdString clock, IdString port, DelayInfo &setup,
-                                     DelayInfo &hold) const
+void Arch::get_setuphold_from_tmg_db(IdString tctype, IdString clock, IdString port, DelayPair &setup,
+                                     DelayPair &hold) const
 {
     for (auto &tc : speed_grade->cell_timings) {
         if (tc.cell_type == tctype.index) {
@@ -764,7 +763,7 @@ void Arch::get_setuphold_from_tmg_db(IdString tctype, IdString clock, IdString p
     NPNR_ASSERT_FALSE("failed to find timing cell in db");
 }
 
-bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
+bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const
 {
     // Data for -8 grade
     if (cell->type == id_TRELLIS_SLICE) {
@@ -779,15 +778,13 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
             (fromPort == id_B0 && toPort == id_WADO1) || (fromPort == id_B1 && toPort == id_WDO3) ||
             (fromPort == id_C0 && toPort == id_WADO2) || (fromPort == id_C1 && toPort == id_WDO0) ||
             (fromPort == id_D0 && toPort == id_WADO0) || (fromPort == id_D1 && toPort == id_WDO2)) {
-            delay.min_delay = 0;
-            delay.max_delay = 0;
+            delay = DelayQuad(0);
             return true;
         }
         return false;
     } else if (cell->type == id_DCCA) {
         if (fromPort == id_CLKI && toPort == id_CLKO) {
-            delay.min_delay = 0;
-            delay.max_delay = 0;
+            delay = DelayQuad(0);
             return true;
         }
         return false;
@@ -987,9 +984,9 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
 TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
 {
     TimingClockingInfo info;
-    info.setup = getDelayFromNS(0);
-    info.hold = getDelayFromNS(0);
-    info.clockToQ = getDelayFromNS(0);
+    info.setup = DelayPair(0);
+    info.hold = DelayPair(0);
+    info.clockToQ = DelayQuad(0);
     if (cell->type == id_TRELLIS_SLICE) {
         int sd0 = cell->sliceInfo.sd0, sd1 = cell->sliceInfo.sd1;
         if (port == id_WD0 || port == id_WD1 || port == id_WAD0 || port == id_WAD1 || port == id_WAD2 ||
@@ -1058,26 +1055,26 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
         else if (prefix == "CH1_FF_RX")
             info.clock_port = id_CH1_FF_RXI_CLK;
         if (cell->ports.at(port).type == PORT_OUT) {
-            info.clockToQ = getDelayFromNS(0.7);
+            info.clockToQ = DelayQuad(getDelayFromNS(0.7));
         } else {
-            info.setup = getDelayFromNS(1);
-            info.hold = getDelayFromNS(0);
+            info.setup = DelayPair(getDelayFromNS(1));
+            info.hold = DelayPair(getDelayFromNS(0));
         }
     } else if (cell->type == id_IOLOGIC || cell->type == id_SIOLOGIC) {
         info.clock_port = id_CLK;
         if (cell->ports.at(port).type == PORT_OUT) {
-            info.clockToQ = getDelayFromNS(0.5);
+            info.clockToQ = DelayQuad(getDelayFromNS(0.5));
         } else {
-            info.setup = getDelayFromNS(0.1);
-            info.hold = getDelayFromNS(0);
+            info.setup = DelayPair(getDelayFromNS(0.1));
+            info.hold = DelayPair(getDelayFromNS(0));
         }
     } else if (cell->type == id_DQSBUFM) {
         info.clock_port = id_SCLK;
         if (port == id_DATAVALID) {
-            info.clockToQ = getDelayFromNS(0.2);
+            info.clockToQ = DelayQuad(getDelayFromNS(0.2));
         } else if (port == id_READ0 || port == id_READ1) {
-            info.setup = getDelayFromNS(0.5);
-            info.hold = getDelayFromNS(-0.4);
+            info.setup = DelayPair(getDelayFromNS(0.5));
+            info.hold = DelayPair(getDelayFromNS(-0.4));
         } else {
             NPNR_ASSERT_FALSE("unknown DQSBUFM register port");
         }
diff --git a/ecp5/arch.h b/ecp5/arch.h
index 83928256..f1da870a 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -643,13 +643,7 @@ struct Arch : BaseArch<ArchRanges>
         BaseArch::unbindWire(wire);
     }
 
-    DelayInfo getWireDelay(WireId wire) const override
-    {
-        DelayInfo delay;
-        delay.min_delay = 0;
-        delay.max_delay = 0;
-        return delay;
-    }
+    DelayQuad getWireDelay(WireId wire) const override { return DelayQuad(0); }
 
     WireRange getWires() const override
     {
@@ -729,21 +723,20 @@ struct Arch : BaseArch<ArchRanges>
         return wire;
     }
 
-    DelayInfo getPipDelay(PipId pip) const override
+    DelayQuad getPipDelay(PipId pip) const override
     {
-        DelayInfo delay;
         NPNR_ASSERT(pip != PipId());
         int fanout = 0;
         auto fnd_fanout = wire_fanout.find(getPipSrcWire(pip));
         if (fnd_fanout != wire_fanout.end())
             fanout = fnd_fanout->second;
-        delay.min_delay =
+        delay_t min_dly =
                 speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].min_base_delay +
                 fanout * speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].min_fanout_adder;
-        delay.max_delay =
+        delay_t max_dly =
                 speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].max_base_delay +
                 fanout * speed_grade->pip_classes[loc_info(pip)->pip_data[pip.index].timing_class].max_fanout_adder;
-        return delay;
+        return DelayQuad(min_dly, max_dly);
     }
 
     PipRange getPipsDownhill(WireId wire) const override
@@ -821,13 +814,7 @@ struct Arch : BaseArch<ArchRanges>
     delay_t getDelayEpsilon() const override { return 20; }
     delay_t getRipupDelayPenalty() const override;
     float getDelayNS(delay_t v) const override { return v * 0.001; }
-    DelayInfo getDelayFromNS(float ns) const override
-    {
-        DelayInfo del;
-        del.min_delay = delay_t(ns * 1000);
-        del.max_delay = delay_t(ns * 1000);
-        return del;
-    }
+    delay_t getDelayFromNS(float ns) const override { return delay_t(ns * 1000); }
     uint32_t getDelayChecksum(delay_t v) const override { return v; }
     bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
 
@@ -850,7 +837,7 @@ struct Arch : BaseArch<ArchRanges>
 
     // Get the delay through a cell from one port to another, returning false
     // if no path exists
-    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const override;
+    bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayQuad &delay) const override;
     // Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
     TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override;
     // Get the TimingClockingInfo of a port
@@ -858,9 +845,9 @@ struct Arch : BaseArch<ArchRanges>
     // Return true if a port is a net
     bool is_global_net(const NetInfo *net) const;
 
-    bool get_delay_from_tmg_db(IdString tctype, IdString from, IdString to, DelayInfo &delay) const;
-    void get_setuphold_from_tmg_db(IdString tctype, IdString clock, IdString port, DelayInfo &setup,
-                                   DelayInfo &hold) const;
+    bool get_delay_from_tmg_db(IdString tctype, IdString from, IdString to, DelayQuad &delay) const;
+    void get_setuphold_from_tmg_db(IdString tctype, IdString clock, IdString port, DelayPair &setup,
+                                   DelayPair &hold) const;
 
     // -------------------------------------------------
     // Placement validity checks
@@ -929,7 +916,7 @@ struct Arch : BaseArch<ArchRanges>
     std::unordered_map<WireId, std::pair<int, int>> wire_loc_overrides;
     void setup_wire_locations();
 
-    mutable std::unordered_map<DelayKey, std::pair<bool, DelayInfo>> celldelay_cache;
+    mutable std::unordered_map<DelayKey, std::pair<bool, DelayQuad>> celldelay_cache;
 
     static const std::string defaultPlacer;
     static const std::vector<std::string> availablePlacers;
diff --git a/ecp5/archdefs.h b/ecp5/archdefs.h
index c8fdf892..732ea99a 100644
--- a/ecp5/archdefs.h
+++ b/ecp5/archdefs.h
@@ -28,28 +28,6 @@ NEXTPNR_NAMESPACE_BEGIN
 
 typedef int delay_t;
 
-struct DelayInfo
-{
-    delay_t min_delay = 0, max_delay = 0;
-
-    delay_t minRaiseDelay() const { return min_delay; }
-    delay_t maxRaiseDelay() const { return max_delay; }
-
-    delay_t minFallDelay() const { return min_delay; }
-    delay_t maxFallDelay() const { return max_delay; }
-
-    delay_t minDelay() const { return min_delay; }
-    delay_t maxDelay() const { return max_delay; }
-
-    DelayInfo operator+(const DelayInfo &other) const
-    {
-        DelayInfo ret;
-        ret.min_delay = this->min_delay + other.min_delay;
-        ret.max_delay = this->max_delay + other.max_delay;
-        return ret;
-    }
-};
-
 // -----------------------------------------------------------------------
 
 // https://bugreports.qt.io/browse/QTBUG-80789
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 60038473..aa7fdd22 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -2851,7 +2851,7 @@ class Ecp5Packer
             NetInfo *from = ci->ports.at(port).net;
             if (from == nullptr || from->clkconstr == nullptr)
                 return false;
-            period = from->clkconstr->period.min_delay;
+            period = from->clkconstr->period.minDelay();
             return true;
         };
 
@@ -2862,7 +2862,7 @@ class Ecp5Packer
             if (to == nullptr)
                 return;
             if (to->clkconstr != nullptr) {
-                if (!equals_epsilon(to->clkconstr->period.min_delay, period) && user_constrained.count(to->name))
+                if (!equals_epsilon(to->clkconstr->period.minDelay(), period) && user_constrained.count(to->name))
                     log_warning(
                             "    Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
                             "%.1f MHz.\n",
@@ -2870,13 +2870,10 @@ class Ecp5Packer
                 return;
             }
             to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
-            to->clkconstr->low.min_delay = period / 2;
-            to->clkconstr->low.max_delay = period / 2;
-            to->clkconstr->high.min_delay = period / 2;
-            to->clkconstr->high.max_delay = period / 2;
-            to->clkconstr->period.min_delay = period;
-            to->clkconstr->period.max_delay = period;
-            log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
+            to->clkconstr->low = DelayPair(period / 2);
+            to->clkconstr->high = DelayPair(period / 2);
+            to->clkconstr->period = DelayPair(period);
+            log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
                      to->name.c_str(ctx));
             changed_nets.insert(to->name);
         };
@@ -2888,21 +2885,24 @@ class Ecp5Packer
             if (from == nullptr || from->clkconstr == nullptr || to == nullptr)
                 return;
             if (to->clkconstr != nullptr) {
-                if (!equals_epsilon(to->clkconstr->period.min_delay,
-                                    delay_t(from->clkconstr->period.min_delay / ratio)) &&
+                if (!equals_epsilon(to->clkconstr->period.minDelay(),
+                                    delay_t(from->clkconstr->period.minDelay() / ratio)) &&
                     user_constrained.count(to->name))
                     log_warning(
                             "    Overriding derived constraint of %.1f MHz on net %s with user-specified constraint of "
                             "%.1f MHz.\n",
-                            MHz(to->clkconstr->period.min_delay), to->name.c_str(ctx),
-                            MHz(delay_t(from->clkconstr->period.min_delay / ratio)));
+                            MHz(to->clkconstr->period.minDelay()), to->name.c_str(ctx),
+                            MHz(delay_t(from->clkconstr->period.minDelay() / ratio)));
                 return;
             }
             to->clkconstr = std::unique_ptr<ClockConstraint>(new ClockConstraint());
-            to->clkconstr->low = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio);
-            to->clkconstr->high = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio);
-            to->clkconstr->period = ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio);
-            log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.min_delay),
+            to->clkconstr->low =
+                    DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->low.min_delay) / ratio));
+            to->clkconstr->high =
+                    DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->high.min_delay) / ratio));
+            to->clkconstr->period =
+                    DelayPair(ctx->getDelayFromNS(ctx->getDelayNS(from->clkconstr->period.min_delay) / ratio));
+            log_info("    Derived frequency constraint of %.1f MHz for net %s\n", MHz(to->clkconstr->period.minDelay()),
                      to->name.c_str(ctx));
             changed_nets.insert(to->name);
         };