Merge branch 'master' into redist_slack

3 files changed, 115 insertions, 54 deletions

diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 90f88384..d887aa69 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -206,7 +206,7 @@ BelRange Arch::getBelsAtSameTile(BelId bel) const
     return br;
 }
 
-WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
+WireId Arch::getBelPinWire(BelId bel, PortPin pin) const
 {
     WireId ret;
 
@@ -224,6 +224,20 @@ WireId Arch::getWireBelPin(BelId bel, PortPin pin) const
     return ret;
 }
 
+PortType Arch::getBelPinType(BelId bel, PortPin pin) const
+{
+    NPNR_ASSERT(bel != BelId());
+
+    int num_bel_wires = locInfo(bel)->bel_data[bel.index].num_bel_wires;
+    const BelWirePOD *bel_wires = locInfo(bel)->bel_data[bel.index].bel_wires.get();
+
+    for (int i = 0; i < num_bel_wires; i++)
+        if (bel_wires[i].port == pin)
+            return PortType(bel_wires[i].type);
+
+    return PORT_INOUT;
+}
+
 // -----------------------------------------------------------------------
 
 WireId Arch::getWireByName(IdString name) const
@@ -314,6 +328,60 @@ std::string Arch::getBelPackagePin(BelId bel) const
     }
     return "";
 }
+
+std::vector<PortPin> Arch::getBelPins(BelId bel) const
+
+{
+    std::vector<PortPin> ret;
+    NPNR_ASSERT(bel != BelId());
+
+    int num_bel_wires = locInfo(bel)->bel_data[bel.index].num_bel_wires;
+    const BelWirePOD *bel_wires = locInfo(bel)->bel_data[bel.index].bel_wires.get();
+
+    for (int i = 0; i < num_bel_wires; i++)
+        ret.push_back(bel_wires[i].port);
+
+    return ret;
+}
+
+BelId Arch::getBelByLocation(Loc loc) const
+{
+    if (loc.x >= chip_info->width || loc.y >= chip_info->height)
+        return BelId();
+    const LocationTypePOD &locI = chip_info->locations[chip_info->location_type[loc.y * chip_info->width + loc.x]];
+    for (int i = 0; i < locI.num_bels; i++) {
+        if (locI.bel_data[i].z == loc.z) {
+            BelId bi;
+            bi.location.x = loc.x;
+            bi.location.y = loc.y;
+            bi.index = i;
+            return bi;
+        }
+    }
+    return BelId();
+}
+
+BelRange Arch::getBelsByTile(int x, int y) const
+{
+    BelRange br;
+
+    int num_bels = 0;
+
+    if (x < chip_info->width && y < chip_info->height) {
+        const LocationTypePOD &locI = chip_info->locations[chip_info->location_type[y * chip_info->width + x]];
+        num_bels = locI.num_bels;
+    }
+
+    br.b.cursor_tile = y * chip_info->width + x;
+    br.e.cursor_tile = y * chip_info->width + x;
+    br.b.cursor_index = 0;
+    br.e.cursor_index = num_bels - 1;
+    br.b.chip = chip_info;
+    br.e.chip = chip_info;
+    ++br.e;
+    return br;
+}
+
 // -----------------------------------------------------------------------
 
 void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
@@ -325,7 +393,7 @@ void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
 
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
-    return abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y);
+    return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
 }
 
 delay_t Arch::getBudgetOverride(const PortRef& pr, delay_t v) const
diff --git a/ecp5/arch.h b/ecp5/arch.h
index ec98d029..38362d6b 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -50,11 +50,13 @@ NPNR_PACKED_STRUCT(struct BelWirePOD {
     LocationPOD rel_wire_loc;
     int32_t wire_index;
     PortPin port;
+    int32_t type;
 });
 
 NPNR_PACKED_STRUCT(struct BelInfoPOD {
     RelPtr<char> name;
     BelType type;
+    int32_t z;
     int32_t num_bel_wires;
     RelPtr<BelWirePOD> bel_wires;
 });
@@ -84,9 +86,8 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
     int32_t num_uphill, num_downhill;
     RelPtr<PipLocatorPOD> pips_uphill, pips_downhill;
 
-    int32_t num_bels_downhill;
-    BelPortPOD bel_uphill;
-    RelPtr<BelPortPOD> bels_downhill;
+    int32_t num_bel_pins;
+    RelPtr<BelPortPOD> bel_pins;
 });
 
 NPNR_PACKED_STRUCT(struct LocationTypePOD {
@@ -387,6 +388,11 @@ struct Arch : BaseCtx
 
     IdString portPinToId(PortPin type) const;
     PortPin portPinFromId(IdString id) const;
+    // -------------------------------------------------
+
+    int getGridDimX() const { return chip_info->width; };
+    int getGridDimY() const { return chip_info->height; };
+    int getTileDimZ(int, int) const { return 4; };
 
     // -------------------------------------------------
 
@@ -425,6 +431,20 @@ struct Arch : BaseCtx
         bel_to_cell[bel] = IdString();
     }
 
+    Loc getBelLocation(BelId bel) const
+    {
+        Loc loc;
+        loc.x = bel.location.x;
+        loc.y = bel.location.y;
+        loc.z = locInfo(bel)->bel_data[bel.index].z;
+        return loc;
+    }
+
+    BelId getBelByLocation(Loc loc) const;
+    BelRange getBelsByTile(int x, int y) const;
+
+    bool getBelGlobalBuf(BelId bel) const { return false; }
+
     bool checkBelAvail(BelId bel) const
     {
         NPNR_ASSERT(bel != BelId());
@@ -462,20 +482,6 @@ struct Arch : BaseCtx
         return range;
     }
 
-    BelRange getBelsByType(BelType type) const
-    {
-        BelRange range;
-// FIXME
-#if 0
-        if (type == "TYPE_A") {
-			range.b.cursor = bels_type_a_begin;
-			range.e.cursor = bels_type_a_end;
-		}
-		...
-#endif
-        return range;
-    }
-
     BelRange getBelsAtSameTile(BelId bel) const;
 
     BelType getBelType(BelId bel) const
@@ -484,33 +490,21 @@ struct Arch : BaseCtx
         return locInfo(bel)->bel_data[bel.index].type;
     }
 
-    WireId getWireBelPin(BelId bel, PortPin pin) const;
-
-    BelPin getBelPinUphill(WireId wire) const
-    {
-        BelPin ret;
-        NPNR_ASSERT(wire != WireId());
-
-        if (locInfo(wire)->wire_data[wire.index].bel_uphill.bel_index >= 0) {
-            ret.bel.index = locInfo(wire)->wire_data[wire.index].bel_uphill.bel_index;
-            ret.bel.location = wire.location + locInfo(wire)->wire_data[wire.index].bel_uphill.rel_bel_loc;
-            ret.pin = locInfo(wire)->wire_data[wire.index].bel_uphill.port;
-        }
-
-        return ret;
-    }
+    WireId getBelPinWire(BelId bel, PortPin pin) const;
 
-    BelPinRange getBelPinsDownhill(WireId wire) const
+    BelPinRange getWireBelPins(WireId wire) const
     {
         BelPinRange range;
         NPNR_ASSERT(wire != WireId());
-        range.b.ptr = locInfo(wire)->wire_data[wire.index].bels_downhill.get();
+        range.b.ptr = locInfo(wire)->wire_data[wire.index].bel_pins.get();
         range.b.wire_loc = wire.location;
-        range.e.ptr = range.b.ptr + locInfo(wire)->wire_data[wire.index].num_bels_downhill;
+        range.e.ptr = range.b.ptr + locInfo(wire)->wire_data[wire.index].num_bel_pins;
         range.e.wire_loc = wire.location;
         return range;
     }
 
+    std::vector<PortPin> getBelPins(BelId bel) const;
+
     // -------------------------------------------------
 
     WireId getWireByName(IdString name) const;
@@ -581,6 +575,7 @@ struct Arch : BaseCtx
     DelayInfo getWireDelay(WireId wire) const
     {
         DelayInfo delay;
+        delay.delay = 0;
         return delay;
     }
 
@@ -694,7 +689,7 @@ struct Arch : BaseCtx
     {
         DelayInfo delay;
         NPNR_ASSERT(pip != PipId());
-        delay.delay = locInfo(pip)->pip_data[pip.index].delay;
+        delay.delay = locInfo(pip)->pip_data[pip.index].delay * 100;
         return delay;
     }
 
@@ -739,6 +734,8 @@ struct Arch : BaseCtx
     BelId getPackagePinBel(const std::string &pin) const;
     std::string getBelPackagePin(BelId bel) const;
 
+    PortType getBelPinType(BelId bel, PortPin pin) const;
+
     // -------------------------------------------------
 
     GroupId getGroupByName(IdString name) const { return GroupId(); }
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py
index af5386e7..b5cd53f1 100755
--- a/ecp5/trellis_import.py
+++ b/ecp5/trellis_import.py
@@ -401,12 +401,12 @@ def write_database(dev_name, ddrg, endianness):
                     for up in wire.arcsUphill:
                         write_loc(up.rel, "rel_loc")
                         bba.u32(up.id, "index")
-                if len(wire.belsDownhill) > 0:
-                    bba.l("loc%d_wire%d_downbels" % (idx, wire_idx), "BelPortPOD")
-                    for db in wire.belsDownhill:
-                        write_loc(db.bel.rel, "rel_bel_loc")
-                        bba.u32(db.bel.id, "bel_index")
-                        bba.u32(portpins[ddrg.to_str(db.pin)], "port")
+                if len(wire.belPins) > 0:
+                    bba.l("loc%d_wire%d_belpins" % (idx, wire_idx), "BelPortPOD")
+                    for bp in wire.belPins:
+                        write_loc(bp.bel.rel, "rel_bel_loc")
+                        bba.u32(bp.bel.id, "bel_index")
+                        bba.u32(portpins[ddrg.to_str(bp.pin)], "port")
             bba.l("loc%d_wires" % idx, "WireInfoPOD")
             for wire_idx in range(len(loctype.wires)):
                 wire = loctype.wires[wire_idx]
@@ -415,28 +415,24 @@ def write_database(dev_name, ddrg, endianness):
                 bba.u32(len(wire.arcsDownhill), "num_downhill")
                 bba.r("loc%d_wire%d_uppips" % (idx, wire_idx) if len(wire.arcsUphill) > 0 else None, "pips_uphill")
                 bba.r("loc%d_wire%d_downpips" % (idx, wire_idx) if len(wire.arcsDownhill) > 0 else None, "pips_downhill")
-                bba.u32(len(wire.belsDownhill), "num_bels_downhill")
-                write_loc(wire.belUphill.bel.rel, "uphill_bel_loc")
-                if wire.belUphill.pin != -1:
-                    bba.u32(wire.belUphill.bel.id, "uphill_bel_idx")
-                    bba.u32(portpins[ddrg.to_str(wire.belUphill.pin)], "uphill_bel_pin")
-                else:
-                    bba.u32(0xFFFFFFFF, "bel_uphill.bel_index")
-                    bba.u32(0, "bel_uphill.port")
-                bba.r("loc%d_wire%d_downbels" % (idx, wire_idx) if len(wire.belsDownhill) > 0 else None, "bels_downhill")
+                bba.u32(len(wire.belPins), "num_bel_pins")
+                bba.r("loc%d_wire%d_belpins" % (idx, wire_idx) if len(wire.belPins) > 0 else None, "bel_pins")
+
         if len(loctype.bels) > 0:
             for bel_idx in range(len(loctype.bels)):
                 bel = loctype.bels[bel_idx]
-                bba.l("loc%d_bel%d_wires" % (idx, bel_idx), "BelPortPOD")
+                bba.l("loc%d_bel%d_wires" % (idx, bel_idx), "BelWirePOD")
                 for pin in bel.wires:
                     write_loc(pin.wire.rel, "rel_wire_loc")
                     bba.u32(pin.wire.id, "wire_index")
                     bba.u32(portpins[ddrg.to_str(pin.pin)], "port")
+                    bba.u32(int(pin.dir), "dir")
             bba.l("loc%d_bels" % idx, "BelInfoPOD")
             for bel_idx in range(len(loctype.bels)):
                 bel = loctype.bels[bel_idx]
                 bba.s(ddrg.to_str(bel.name), "name")
                 bba.u32(bel_types[ddrg.to_str(bel.type)], "type")
+                bba.u32(bel.z, "z")
                 bba.u32(len(bel.wires), "num_bel_wires")
                 bba.r("loc%d_bel%d_wires" % (idx, bel_idx), "bel_wires")