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authorgatecat <gatecat@ds0.me>2022-02-16 18:13:22 +0000
committerGitHub <noreply@github.com>2022-02-16 18:13:22 +0000
commit61d1db16be2c68cf6ae8b4d2ff3266b5c7086ad2 (patch)
tree379b38c06745919df0e87c1be1410e16793b0925 /ecp5
parent25c47e5b7e12d232cac9408b7d6d339ee11793b7 (diff)
parent76683a1e3c123d28deff750c38467c6377936879 (diff)
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Merge pull request #918 from YosysHQ/gatecat/netlist-ii
Refactor pt2, barnacle cleanup
Diffstat (limited to 'ecp5')
-rw-r--r--ecp5/arch.cc37
-rw-r--r--ecp5/arch_place.cc2
-rw-r--r--ecp5/bitstream.cc495
-rw-r--r--ecp5/cells.cc434
-rw-r--r--ecp5/cells.h33
-rw-r--r--ecp5/constids.inc510
-rw-r--r--ecp5/dcu_bitstream.h588
-rw-r--r--ecp5/globals.cc14
-rw-r--r--ecp5/lpf.cc2
-rw-r--r--ecp5/main.cc2
-rw-r--r--ecp5/pack.cc883
11 files changed, 1675 insertions, 1325 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 2e453f2a..3d20badb 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -202,25 +202,25 @@ std::string Arch::get_full_chip_name() const
IdString Arch::archArgsToId(ArchArgs args) const
{
if (args.type == ArchArgs::LFE5U_12F)
- return id("lfe5u_12f");
+ return id_lfe5u_12f;
if (args.type == ArchArgs::LFE5U_25F)
- return id("lfe5u_25f");
+ return id_lfe5u_25f;
if (args.type == ArchArgs::LFE5U_45F)
- return id("lfe5u_45f");
+ return id_lfe5u_45f;
if (args.type == ArchArgs::LFE5U_85F)
- return id("lfe5u_85f");
+ return id_lfe5u_85f;
if (args.type == ArchArgs::LFE5UM_25F)
- return id("lfe5um_25f");
+ return id_lfe5um_25f;
if (args.type == ArchArgs::LFE5UM_45F)
- return id("lfe5um_45f");
+ return id_lfe5um_45f;
if (args.type == ArchArgs::LFE5UM_85F)
- return id("lfe5um_85f");
+ return id_lfe5um_85f;
if (args.type == ArchArgs::LFE5UM5G_25F)
- return id("lfe5um5g_25f");
+ return id_lfe5um5g_25f;
if (args.type == ArchArgs::LFE5UM5G_45F)
- return id("lfe5um5g_45f");
+ return id_lfe5um5g_45f;
if (args.type == ArchArgs::LFE5UM5G_85F)
- return id("lfe5um5g_85f");
+ return id_lfe5um5g_85f;
return IdString();
}
@@ -586,7 +586,7 @@ delay_t Arch::getRipupDelayPenalty() const { return 400; }
bool Arch::place()
{
- std::string placer = str_or_default(settings, id("placer"), defaultPlacer);
+ std::string placer = str_or_default(settings, id_placer, defaultPlacer);
if (placer == "heap") {
PlacerHeapCfg cfg(getCtx());
@@ -612,7 +612,7 @@ bool Arch::place()
for (auto &cell : cells)
cell.second->belStrength = STRENGTH_LOCKED;
- getCtx()->settings[getCtx()->id("place")] = 1;
+ getCtx()->settings[id_place] = 1;
archInfoToAttributes();
return true;
@@ -620,7 +620,7 @@ bool Arch::place()
bool Arch::route()
{
- std::string router = str_or_default(settings, id("router"), defaultRouter);
+ std::string router = str_or_default(settings, id_router, defaultRouter);
disable_router_lutperm = getCtx()->setting<bool>("arch.disable_router_lutperm", false);
@@ -639,7 +639,7 @@ bool Arch::route()
log_error("ECP5 architecture does not support router '%s'\n", router.c_str());
}
- getCtx()->settings[getCtx()->id("route")] = 1;
+ getCtx()->settings[id_route] = 1;
archInfoToAttributes();
return result;
}
@@ -1033,12 +1033,12 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
get_setuphold_from_tmg_db(id_SDPRAME, id_WCK, port, info.setup, info.hold);
} else if (port == id_DI0 || port == id_DI1 || port == id_CE || port == id_LSR || (sd0 == 0 && port == id_M0) ||
(sd1 == 0 && port == id_M1)) {
- info.edge = cell->sliceInfo.clkmux == id("INV") ? FALLING_EDGE : RISING_EDGE;
+ info.edge = cell->sliceInfo.clkmux == id_INV ? FALLING_EDGE : RISING_EDGE;
info.clock_port = id_CLK;
get_setuphold_from_tmg_db(id_SLOGICB, id_CLK, port, info.setup, info.hold);
} else {
- info.edge = cell->sliceInfo.clkmux == id("INV") ? FALLING_EDGE : RISING_EDGE;
+ info.edge = cell->sliceInfo.clkmux == id_INV ? FALLING_EDGE : RISING_EDGE;
info.clock_port = id_CLK;
bool is_path = get_delay_from_tmg_db(id_SLOGICB, id_CLK, port, info.clockToQ);
NPNR_ASSERT(is_path);
@@ -1070,8 +1070,7 @@ TimingClockingInfo Arch::getPortClockingInfo(const CellInfo *cell, IdString port
} else {
info.clock_port = half_clock;
}
- info.edge = (str_or_default(cell->params, info.clock_port == id_CLKB ? id("CLKBMUX") : id("CLKAMUX"), "CLK") ==
- "INV")
+ info.edge = (str_or_default(cell->params, info.clock_port == id_CLKB ? id_CLKBMUX : id_CLKAMUX, "CLK") == "INV")
? FALLING_EDGE
: RISING_EDGE;
if (cell->ports.at(port).type == PORT_OUT) {
@@ -1298,7 +1297,7 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
std::vector<std::pair<IdString, std::string>> ret;
auto &wi = loc_info(wire)->wire_data[wire.index];
- ret.push_back(std::make_pair(id("TILE_WIRE_ID"), stringf("%d", wi.tile_wire)));
+ ret.push_back(std::make_pair(id_TILE_WIRE_ID, stringf("%d", wi.tile_wire)));
return ret;
}
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index 3cc6d252..a1f8aa1f 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -150,7 +150,7 @@ void Arch::permute_luts()
for (auto &cell : cells) {
CellInfo *ci = cell.second.get();
- if (ci->type == id_TRELLIS_SLICE && str_or_default(ci->params, id("MODE"), "LOGIC") == "LOGIC") {
+ if (ci->type == id_TRELLIS_SLICE && str_or_default(ci->params, id_MODE, "LOGIC") == "LOGIC") {
proc_lut(ci, 0);
proc_lut(ci, 1);
}
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc
index de6c711e..11a855ec 100644
--- a/ecp5/bitstream.cc
+++ b/ecp5/bitstream.cc
@@ -723,10 +723,10 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
- if (ci->bel != BelId() && ci->type == ctx->id("TRELLIS_IO")) {
+ if (ci->bel != BelId() && ci->type == id_TRELLIS_IO) {
int bank = ctx->get_pio_bel_bank(ci->bel);
- std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
- std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
+ std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
+ std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
if (dir != "INPUT" || is_referenced(ioType_from_str(iotype))) {
IOVoltage vcc = get_vccio(ioType_from_str(iotype));
@@ -835,71 +835,65 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx));
}
BelId bel = ci->bel;
- if (ci->type == ctx->id("TRELLIS_SLICE")) {
+ if (ci->type == id_TRELLIS_SLICE) {
pool<IdString> used_phys_pins;
std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
std::string slice = ctx->loc_info(bel)->bel_data[bel.index].name.get();
- int lut0_init = int_or_default(ci->params, ctx->id("LUT0_INITVAL"));
- int lut1_init = int_or_default(ci->params, ctx->id("LUT1_INITVAL"));
+ int lut0_init = int_or_default(ci->params, id_LUT0_INITVAL);
+ int lut1_init = int_or_default(ci->params, id_LUT1_INITVAL);
cc.tiles[tname].add_word(slice + ".K0.INIT",
int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, 0, lut0_init), 16));
cc.tiles[tname].add_word(slice + ".K1.INIT",
int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, 1, lut1_init), 16));
- cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, ctx->id("MODE"), "LOGIC"));
- cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
- cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, ctx->id("REG0_SD"), "0"));
- cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, ctx->id("REG1_SD"), "0"));
- cc.tiles[tname].add_enum(slice + ".REG0.REGSET",
- str_or_default(ci->params, ctx->id("REG0_REGSET"), "RESET"));
- cc.tiles[tname].add_enum(slice + ".REG1.REGSET",
- str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET"));
- cc.tiles[tname].add_enum(slice + ".REG0.LSRMODE",
- str_or_default(ci->params, ctx->id("REG0_LSRMODE"), "LSR"));
- cc.tiles[tname].add_enum(slice + ".REG1.LSRMODE",
- str_or_default(ci->params, ctx->id("REG1_LSRMODE"), "LSR"));
- cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1"));
+ cc.tiles[tname].add_enum(slice + ".MODE", str_or_default(ci->params, id_MODE, "LOGIC"));
+ cc.tiles[tname].add_enum(slice + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+ cc.tiles[tname].add_enum(slice + ".REG0.SD", intstr_or_default(ci->params, id_REG0_SD, "0"));
+ cc.tiles[tname].add_enum(slice + ".REG1.SD", intstr_or_default(ci->params, id_REG1_SD, "0"));
+ cc.tiles[tname].add_enum(slice + ".REG0.REGSET", str_or_default(ci->params, id_REG0_REGSET, "RESET"));
+ cc.tiles[tname].add_enum(slice + ".REG1.REGSET", str_or_default(ci->params, id_REG1_REGSET, "RESET"));
+ cc.tiles[tname].add_enum(slice + ".REG0.LSRMODE", str_or_default(ci->params, id_REG0_LSRMODE, "LSR"));
+ cc.tiles[tname].add_enum(slice + ".REG1.LSRMODE", str_or_default(ci->params, id_REG1_LSRMODE, "LSR"));
+ cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, id_CEMUX, "1"));
if (ci->sliceInfo.using_dff) {
NetInfo *lsrnet = nullptr;
- if (ci->ports.find(ctx->id("LSR")) != ci->ports.end() && ci->ports.at(ctx->id("LSR")).net != nullptr)
- lsrnet = ci->ports.at(ctx->id("LSR")).net;
+ if (ci->ports.find(id_LSR) != ci->ports.end() && ci->ports.at(id_LSR).net != nullptr)
+ lsrnet = ci->ports.at(id_LSR).net;
if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR0")) == lsrnet) {
- cc.tiles[tname].add_enum("LSR0.SRMODE",
- str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
- cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
+ cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+ cc.tiles[tname].add_enum("LSR0.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
}
if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "LSR1")) == lsrnet) {
- cc.tiles[tname].add_enum("LSR1.SRMODE",
- str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
- cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, ctx->id("LSRMUX"), "LSR"));
+ cc.tiles[tname].add_enum("LSR1.SRMODE", str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
+ cc.tiles[tname].add_enum("LSR1.LSRMUX", str_or_default(ci->params, id_LSRMUX, "LSR"));
}
NetInfo *clknet = nullptr;
- if (ci->ports.find(ctx->id("CLK")) != ci->ports.end() && ci->ports.at(ctx->id("CLK")).net != nullptr)
- clknet = ci->ports.at(ctx->id("CLK")).net;
+ if (ci->ports.find(id_CLK) != ci->ports.end() && ci->ports.at(id_CLK).net != nullptr)
+ clknet = ci->ports.at(id_CLK).net;
if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK0")) == clknet) {
- cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, ctx->id("CLKMUX"), "CLK"));
+ cc.tiles[tname].add_enum("CLK0.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
}
if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
- cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, ctx->id("CLKMUX"), "CLK"));
+ cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
}
}
- if (str_or_default(ci->params, ctx->id("MODE"), "LOGIC") == "CCU2") {
+ if (str_or_default(ci->params, id_MODE, "LOGIC") == "CCU2") {
cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0",
- str_or_default(ci->params, ctx->id("CCU2_INJECT1_0"), "YES"));
+ str_or_default(ci->params, id_CCU2_INJECT1_0, "YES"));
cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1",
- str_or_default(ci->params, ctx->id("CCU2_INJECT1_1"), "YES"));
+ str_or_default(ci->params, id_CCU2_INJECT1_1, "YES"));
} else {
// Don't interfere with cascade mux wiring
cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_0", "_NONE_");
cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_1", "_NONE_");
}
- if (str_or_default(ci->params, ctx->id("MODE"), "LOGIC") == "DPRAM" && slice == "SLICEA") {
- cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, ctx->id("WREMUX"), "WRE"));
+ if (str_or_default(ci->params, id_MODE, "LOGIC") == "DPRAM" && slice == "SLICEA") {
+ cc.tiles[tname].add_enum(slice + ".WREMUX", str_or_default(ci->params, id_WREMUX, "WRE"));
- std::string wckmux = str_or_default(ci->params, ctx->id("WCKMUX"), "WCK");
+ std::string wckmux = str_or_default(ci->params, id_WCKMUX, "WCK");
wckmux = (wckmux == "WCK") ? "CLK" : wckmux;
cc.tiles[tname].add_enum("CLK1.CLKMUX", wckmux);
}
@@ -912,10 +906,10 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
// TODO: CLKMUX
- } else if (ci->type == ctx->id("TRELLIS_IO")) {
+ } else if (ci->type == id_TRELLIS_IO) {
std::string pio = ctx->loc_info(bel)->bel_data[bel.index].name.get();
- std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33");
- std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT");
+ std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
+ std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
std::string pio_tile = get_pio_tile(ctx, bel);
std::string pic_tile = get_pic_tile(ctx, bel);
cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
@@ -950,10 +944,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
} else if (is_referenced(ioType_from_str(iotype))) {
cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
}
- if (dir != "INPUT" &&
- (ci->ports.find(ctx->id("T")) == ci->ports.end() || ci->ports.at(ctx->id("T")).net == nullptr) &&
- (ci->ports.find(ctx->id("IOLTO")) == ci->ports.end() ||
- ci->ports.at(ctx->id("IOLTO")).net == nullptr)) {
+ if (dir != "INPUT" && (ci->ports.find(id_T) == ci->ports.end() || ci->ports.at(id_T).net == nullptr) &&
+ (ci->ports.find(id_IOLTO) == ci->ports.end() || ci->ports.at(id_IOLTO).net == nullptr)) {
// Tie tristate low if unconnected for outputs or bidir
WireId jpt_wire = ctx->get_wire_by_loc_basename(bel.location, fmt_str("JPADDT" << pio.back()));
PipId jpt_pip = *ctx->getPipsUphill(jpt_wire).begin();
@@ -964,31 +956,29 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
if ((dir == "INPUT" || dir == "BIDIR") && !is_differential(ioType_from_str(iotype)) &&
!is_referenced(ioType_from_str(iotype))) {
- cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS",
- str_or_default(ci->attrs, ctx->id("HYSTERESIS"), "ON"));
+ cc.tiles[pio_tile].add_enum(pio + ".HYSTERESIS", str_or_default(ci->attrs, id_HYSTERESIS, "ON"));
}
- if (ci->attrs.count(ctx->id("SLEWRATE")) && !is_referenced(ioType_from_str(iotype)))
- cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, ctx->id("SLEWRATE"), "SLOW"));
- if (ci->attrs.count(ctx->id("PULLMODE")))
- cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, ctx->id("PULLMODE"), "NONE"));
- if (ci->attrs.count(ctx->id("DIFFRESISTOR")))
- cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR",
- str_or_default(ci->attrs, ctx->id("DIFFRESISTOR"), "OFF"));
- if (ci->attrs.count(ctx->id("CLAMP")))
- cc.tiles[pio_tile].add_enum(pio + ".CLAMP", str_or_default(ci->attrs, ctx->id("CLAMP"), "OFF"));
-
- if (ci->attrs.count(ctx->id("DRIVE"))) {
+ if (ci->attrs.count(id_SLEWRATE) && !is_referenced(ioType_from_str(iotype)))
+ cc.tiles[pio_tile].add_enum(pio + ".SLEWRATE", str_or_default(ci->attrs, id_SLEWRATE, "SLOW"));
+ if (ci->attrs.count(id_PULLMODE))
+ cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", str_or_default(ci->attrs, id_PULLMODE, "NONE"));
+ if (ci->attrs.count(id_DIFFRESISTOR))
+ cc.tiles[pio_tile].add_enum(pio + ".DIFFRESISTOR", str_or_default(ci->attrs, id_DIFFRESISTOR, "OFF"));
+ if (ci->attrs.count(id_CLAMP))
+ cc.tiles[pio_tile].add_enum(pio + ".CLAMP", str_or_default(ci->attrs, id_CLAMP, "OFF"));
+
+ if (ci->attrs.count(id_DRIVE)) {
static bool drive_3v3_warning_done = false;
if (iotype == "LVCMOS33") {
- cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "8"));
+ cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "8"));
} else if (iotype == "LVCMOS33D") {
if (bel.location.y == 0) {
// Pseudo differential top IO
NPNR_ASSERT(dir == "OUTPUT");
NPNR_ASSERT(pio == "PIOA");
std::string cpio_tile = get_comp_pio_tile(ctx, bel);
- cc.tiles[pio_tile].add_enum("PIOA.DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
- cc.tiles[cpio_tile].add_enum("PIOB.DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
+ cc.tiles[pio_tile].add_enum("PIOA.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
+ cc.tiles[cpio_tile].add_enum("PIOB.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
} else {
std::string other;
if (pio == "PIOA")
@@ -997,9 +987,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
other = "PIOD";
else
log_error("cannot set DRIVE on differential IO at location %s\n", pio.c_str());
- cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
- cc.tiles[pio_tile].add_enum(other + ".DRIVE",
- str_or_default(ci->attrs, ctx->id("DRIVE"), "12"));
+ cc.tiles[pio_tile].add_enum(pio + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
+ cc.tiles[pio_tile].add_enum(other + ".DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
}
} else {
if (!drive_3v3_warning_done)
@@ -1007,28 +996,28 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
drive_3v3_warning_done = true;
}
}
- if (ci->attrs.count(ctx->id("TERMINATION"))) {
+ if (ci->attrs.count(id_TERMINATION)) {
auto vccio = get_vccio(ioType_from_str(iotype));
switch (vccio) {
case IOVoltage::VCC_1V8:
cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V8",
- str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+ str_or_default(ci->attrs, id_TERMINATION, "OFF"));
break;
case IOVoltage::VCC_1V5:
cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V5",
- str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+ str_or_default(ci->attrs, id_TERMINATION, "OFF"));
break;
case IOVoltage::VCC_1V35:
cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V35",
- str_or_default(ci->attrs, ctx->id("TERMINATION"), "OFF"));
+ str_or_default(ci->attrs, id_TERMINATION, "OFF"));
break;
default:
log_error("TERMINATION is not supported with Vcc = %s (on PIO %s)\n",
iovoltage_to_str(vccio).c_str(), ci->name.c_str(ctx));
}
}
- if (ci->attrs.count(ctx->id("OPENDRAIN"))) {
- cc.tiles[pio_tile].add_enum(pio + ".OPENDRAIN", str_or_default(ci->attrs, ctx->id("OPENDRAIN"), "OFF"));
+ if (ci->attrs.count(id_OPENDRAIN)) {
+ cc.tiles[pio_tile].add_enum(pio + ".OPENDRAIN", str_or_default(ci->attrs, id_OPENDRAIN, "OFF"));
if (is_differential(ioType_from_str(iotype))) {
std::string other;
if (pio == "PIOA")
@@ -1037,25 +1026,24 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
other = "PIOD";
else
log_error("cannot set OPENDRAIN on differential IO at location %s\n", pio.c_str());
- cc.tiles[pio_tile].add_enum(other + ".OPENDRAIN",
- str_or_default(ci->attrs, ctx->id("OPENDRAIN"), "OFF"));
+ cc.tiles[pio_tile].add_enum(other + ".OPENDRAIN", str_or_default(ci->attrs, id_OPENDRAIN, "OFF"));
}
}
- std::string datamux_oddr = str_or_default(ci->params, ctx->id("DATAMUX_ODDR"), "PADDO");
+ std::string datamux_oddr = str_or_default(ci->params, id_DATAMUX_ODDR, "PADDO");
if (datamux_oddr != "PADDO")
cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_ODDR", datamux_oddr);
- std::string datamux_oreg = str_or_default(ci->params, ctx->id("DATAMUX_OREG"), "PADDO");
+ std::string datamux_oreg = str_or_default(ci->params, id_DATAMUX_OREG, "PADDO");
if (datamux_oreg != "PADDO")
cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_OREG", datamux_oreg);
- std::string datamux_mddr = str_or_default(ci->params, ctx->id("DATAMUX_MDDR"), "PADDO");
+ std::string datamux_mddr = str_or_default(ci->params, id_DATAMUX_MDDR, "PADDO");
if (datamux_mddr != "PADDO")
cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_MDDR", datamux_mddr);
- std::string trimux_tsreg = str_or_default(ci->params, ctx->id("TRIMUX_TSREG"), "PADDT");
+ std::string trimux_tsreg = str_or_default(ci->params, id_TRIMUX_TSREG, "PADDT");
if (trimux_tsreg != "PADDT")
cc.tiles[pic_tile].add_enum(pio + ".TRIMUX_TSREG", trimux_tsreg);
- } else if (ci->type == ctx->id("DCCA")) {
- const NetInfo *cen = get_net_or_empty(ci, ctx->id("CE"));
+ } else if (ci->type == id_DCCA) {
+ const NetInfo *cen = get_net_or_empty(ci, id_CE);
if (cen != nullptr) {
std::string belname = ctx->loc_info(bel)->bel_data[bel.index].name.get();
Loc loc = ctx->getBelLocation(bel);
@@ -1084,12 +1072,12 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tg.config.add_enum(std::string("DCC_") + belname[0] + belname.substr(4) + ".MODE", "DCCA");
cc.tilegroups.push_back(tg);
}
- } else if (ci->type == ctx->id("DCSC")) {
+ } else if (ci->type == id_DCSC) {
std::set<std::string> dcs_tiles{"EBR_CMUX_LL", "EBR_CMUX_UL", "EBR_CMUX_LL_25K", "DSP_CMUX_UL"};
std::string tile = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, dcs_tiles);
std::string dcs = ctx->loc_info(bel)->bel_data[bel.index].name.get();
- cc.tiles[tile].add_enum(dcs + ".DCSMODE", str_or_default(ci->attrs, ctx->id("DCSMODE"), "POS"));
- } else if (ci->type == ctx->id("DP16KD")) {
+ cc.tiles[tile].add_enum(dcs + ".DCSMODE", str_or_default(ci->attrs, id_DCSMODE, "POS"));
+ } else if (ci->type == id_DP16KD) {
TileGroup tg;
Loc loc = ctx->getBelLocation(ci->bel);
tg.tiles = get_bram_tiles(ctx, ci->bel);
@@ -1098,32 +1086,27 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (ci->ramInfo.is_pdp) {
tg.config.add_enum(ebr + ".MODE", "PDPW16KD");
tg.config.add_enum(ebr + ".PDPW16KD.DATA_WIDTH_R",
- intstr_or_default(ci->params, ctx->id("DATA_WIDTH_B"), "36"));
+ intstr_or_default(ci->params, id_DATA_WIDTH_B, "36"));
} else {
tg.config.add_enum(ebr + ".MODE", "DP16KD");
- tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_A",
- intstr_or_default(ci->params, ctx->id("DATA_WIDTH_A"), "18"));
- tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_B",
- intstr_or_default(ci->params, ctx->id("DATA_WIDTH_B"), "18"));
- tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_A",
- str_or_default(ci->params, ctx->id("WRITEMODE_A"), "NORMAL"));
- tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_B",
- str_or_default(ci->params, ctx->id("WRITEMODE_B"), "NORMAL"));
+ tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_A", intstr_or_default(ci->params, id_DATA_WIDTH_A, "18"));
+ tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_B", intstr_or_default(ci->params, id_DATA_WIDTH_B, "18"));
+ tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_A", str_or_default(ci->params, id_WRITEMODE_A, "NORMAL"));
+ tg.config.add_enum(ebr + ".DP16KD.WRITEMODE_B", str_or_default(ci->params, id_WRITEMODE_B, "NORMAL"));
}
- auto csd_a = str_to_bitvector(str_or_default(ci->params, ctx->id("CSDECODE_A"), "0b000"), 3),
- csd_b = str_to_bitvector(str_or_default(ci->params, ctx->id("CSDECODE_B"), "0b000"), 3);
+ auto csd_a = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_A, "0b000"), 3),
+ csd_b = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_B, "0b000"), 3);
- tg.config.add_enum(ebr + ".REGMODE_A", str_or_default(ci->params, ctx->id("REGMODE_A"), "NOREG"));
- tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, ctx->id("REGMODE_B"), "NOREG"));
+ tg.config.add_enum(ebr + ".REGMODE_A", str_or_default(ci->params, id_REGMODE_A, "NOREG"));
+ tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, id_REGMODE_B, "NOREG"));
- tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
+ tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
tg.config.add_enum(ebr + ".ASYNC_RESET_RELEASE",
- str_or_default(ci->params, ctx->id("ASYNC_RESET_RELEASE"), "SYNC"));
- tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+ str_or_default(ci->params, id_ASYNC_RESET_RELEASE, "SYNC"));
+ tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
- tg.config.add_word(ebr + ".WID",
- int_to_bitvector(bit_reverse(int_or_default(ci->attrs, ctx->id("WID"), 0), 9), 9));
+ tg.config.add_word(ebr + ".WID", int_to_bitvector(bit_reverse(int_or_default(ci->attrs, id_WID, 0), 9), 9));
// Tie signals as appropriate
for (auto port : ci->ports) {
@@ -1169,19 +1152,19 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
}
- tg.config.add_enum(ebr + ".CLKAMUX", str_or_default(ci->params, ctx->id("CLKAMUX"), "CLKA"));
- tg.config.add_enum(ebr + ".CLKBMUX", str_or_default(ci->params, ctx->id("CLKBMUX"), "CLKB"));
+ tg.config.add_enum(ebr + ".CLKAMUX", str_or_default(ci->params, id_CLKAMUX, "CLKA"));
+ tg.config.add_enum(ebr + ".CLKBMUX", str_or_default(ci->params, id_CLKBMUX, "CLKB"));
- tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, ctx->id("RSTAMUX"), "RSTA"));
- tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, ctx->id("RSTBMUX"), "RSTB"));
+ tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, id_RSTAMUX, "RSTA"));
+ tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, id_RSTBMUX, "RSTB"));
if (!ci->ramInfo.is_pdp) {
- tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, ctx->id("WEAMUX"), "WEA"));
- tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, ctx->id("WEBMUX"), "WEB"));
+ tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, id_WEAMUX, "WEA"));
+ tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, id_WEBMUX, "WEB"));
}
- tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, ctx->id("CEAMUX"), "CEA"));
- tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, ctx->id("CEBMUX"), "CEB"));
- tg.config.add_enum(ebr + ".OCEAMUX", str_or_default(ci->params, ctx->id("OCEAMUX"), "OCEA"));
- tg.config.add_enum(ebr + ".OCEBMUX", str_or_default(ci->params, ctx->id("OCEBMUX"), "OCEB"));
+ tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, id_CEAMUX, "CEA"));
+ tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, id_CEBMUX, "CEB"));
+ tg.config.add_enum(ebr + ".OCEAMUX", str_or_default(ci->params, id_OCEAMUX, "OCEA"));
+ tg.config.add_enum(ebr + ".OCEBMUX", str_or_default(ci->params, id_OCEBMUX, "OCEB"));
std::reverse(csd_a.begin(), csd_a.end());
std::reverse(csd_b.begin(), csd_b.end());
@@ -1205,7 +1188,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
}
}
}
- int wid = int_or_default(ci->attrs, ctx->id("WID"), 0);
+ int wid = int_or_default(ci->attrs, id_WID, 0);
NPNR_ASSERT(!cc.bram_data.count(wid));
cc.bram_data[wid] = init_data;
cc.tilegroups.push_back(tg);
@@ -1214,33 +1197,30 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
Loc loc = ctx->getBelLocation(ci->bel);
tg.tiles = get_dsp_tiles(ctx, ci->bel);
std::string dsp = "MULT18_" + std::to_string(loc.z);
- tg.config.add_enum(dsp + ".REG_INPUTA_CLK", str_or_default(ci->params, ctx->id("REG_INPUTA_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_INPUTA_CE", str_or_default(ci->params, ctx->id("REG_INPUTA_CE"), "CE0"));
- tg.config.add_enum(dsp + ".REG_INPUTA_RST", str_or_default(ci->params, ctx->id("REG_INPUTA_RST"), "RST0"));
- tg.config.add_enum(dsp + ".REG_INPUTB_CLK", str_or_default(ci->params, ctx->id("REG_INPUTB_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_INPUTB_CE", str_or_default(ci->params, ctx->id("REG_INPUTB_CE"), "CE0"));
- tg.config.add_enum(dsp + ".REG_INPUTB_RST", str_or_default(ci->params, ctx->id("REG_INPUTB_RST"), "RST0"));
- tg.config.add_enum(dsp + ".REG_INPUTC_CLK", str_or_default(ci->params, ctx->id("REG_INPUTC_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_PIPELINE_CLK",
- str_or_default(ci->params, ctx->id("REG_PIPELINE_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_PIPELINE_CE", str_or_default(ci->params, ctx->id("REG_PIPELINE_CE"), "CE0"));
- tg.config.add_enum(dsp + ".REG_PIPELINE_RST",
- str_or_default(ci->params, ctx->id("REG_PIPELINE_RST"), "RST0"));
- tg.config.add_enum(dsp + ".REG_OUTPUT_CLK", str_or_default(ci->params, ctx->id("REG_OUTPUT_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_INPUTA_CLK", str_or_default(ci->params, id_REG_INPUTA_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_INPUTA_CE", str_or_default(ci->params, id_REG_INPUTA_CE, "CE0"));
+ tg.config.add_enum(dsp + ".REG_INPUTA_RST", str_or_default(ci->params, id_REG_INPUTA_RST, "RST0"));
+ tg.config.add_enum(dsp + ".REG_INPUTB_CLK", str_or_default(ci->params, id_REG_INPUTB_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_INPUTB_CE", str_or_default(ci->params, id_REG_INPUTB_CE, "CE0"));
+ tg.config.add_enum(dsp + ".REG_INPUTB_RST", str_or_default(ci->params, id_REG_INPUTB_RST, "RST0"));
+ tg.config.add_enum(dsp + ".REG_INPUTC_CLK", str_or_default(ci->params, id_REG_INPUTC_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_PIPELINE_CLK", str_or_default(ci->params, id_REG_PIPELINE_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_PIPELINE_CE", str_or_default(ci->params, id_REG_PIPELINE_CE, "CE0"));
+ tg.config.add_enum(dsp + ".REG_PIPELINE_RST", str_or_default(ci->params, id_REG_PIPELINE_RST, "RST0"));
+ tg.config.add_enum(dsp + ".REG_OUTPUT_CLK", str_or_default(ci->params, id_REG_OUTPUT_CLK, "NONE"));
if (dsp == "MULT18_0" || dsp == "MULT18_4")
- tg.config.add_enum(dsp + ".REG_OUTPUT_RST",
- str_or_default(ci->params, ctx->id("REG_OUTPUT_RST"), "RST0"));
+ tg.config.add_enum(dsp + ".REG_OUTPUT_RST", str_or_default(ci->params, id_REG_OUTPUT_RST, "RST0"));
- tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, ctx->id("CLK0_DIV"), "ENABLED"));
- tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, ctx->id("CLK1_DIV"), "ENABLED"));
- tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, ctx->id("CLK2_DIV"), "ENABLED"));
- tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, ctx->id("CLK3_DIV"), "ENABLED"));
- tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
- tg.config.add_enum(dsp + ".SOURCEB_MODE", str_or_default(ci->params, ctx->id("SOURCEB_MODE"), "B_SHIFT"));
- tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
+ tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, id_CLK0_DIV, "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, id_CLK1_DIV, "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, id_CLK2_DIV, "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, id_CLK3_DIV, "ENABLED"));
+ tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+ tg.config.add_enum(dsp + ".SOURCEB_MODE", str_or_default(ci->params, id_SOURCEB_MODE, "B_SHIFT"));
+ tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
tg.config.add_enum(dsp + ".MODE", "MULT18X18D");
- if (str_or_default(ci->params, ctx->id("REG_OUTPUT_CLK"), "NONE") == "NONE" && ci->cluster == ClusterId())
+ if (str_or_default(ci->params, id_REG_OUTPUT_CLK, "NONE") == "NONE" && ci->cluster == ClusterId())
tg.config.add_enum(dsp + ".CIBOUT_BYP", "ON");
if (loc.z < 4)
@@ -1264,67 +1244,53 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
Loc loc = ctx->getBelLocation(ci->bel);
tg.tiles = get_dsp_tiles(ctx, ci->bel);
std::string dsp = "ALU54_" + std::to_string(loc.z);
- tg.config.add_enum(dsp + ".REG_INPUTC0_CLK",
- str_or_default(ci->params, ctx->id("REG_INPUTC0_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_INPUTC1_CLK",
- str_or_default(ci->params, ctx->id("REG_INPUTC1_CLK"), "NONE"));
+ tg.config.add_enum(dsp + ".REG_INPUTC0_CLK", str_or_default(ci->params, id_REG_INPUTC0_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_INPUTC1_CLK", str_or_default(ci->params, id_REG_INPUTC1_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CLK",
- str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CE",
- str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_CE"), "CE0"));
+ str_or_default(ci->params, id_REG_OPCODEOP0_0_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CE", str_or_default(ci->params, id_REG_OPCODEOP0_0_CE, "CE0"));
tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_RST",
- str_or_default(ci->params, ctx->id("REG_OPCODEOP0_0_RST"), "RST0"));
+ str_or_default(ci->params, id_REG_OPCODEOP0_0_RST, "RST0"));
tg.config.add_enum(dsp + ".REG_OPCODEOP1_0_CLK",
- str_or_default(ci->params, ctx->id("REG_OPCODEOP1_0_CLK"), "NONE"));
+ str_or_default(ci->params, id_REG_OPCODEOP1_0_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CLK",
- str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_CLK"), "NONE"));
+ str_or_default(ci->params, id_REG_OPCODEOP0_1_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_OPCODEOP1_1_CLK",
- str_or_default(ci->params, ctx->id("REG_OPCODEOP1_1_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CE",
- str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_CE"), "CE0"));
+ str_or_default(ci->params, id_REG_OPCODEOP1_1_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CE", str_or_default(ci->params, id_REG_OPCODEOP0_1_CE, "CE0"));
tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_RST",
- str_or_default(ci->params, ctx->id("REG_OPCODEOP0_1_RST"), "RST0"));
- tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CLK",
- str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CE",
- str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_CE"), "CE0"));
- tg.config.add_enum(dsp + ".REG_OPCODEIN_0_RST",
- str_or_default(ci->params, ctx->id("REG_OPCODEIN_0_RST"), "RST0"));
- tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CLK",
- str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CE",
- str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_CE"), "CE0"));
- tg.config.add_enum(dsp + ".REG_OPCODEIN_1_RST",
- str_or_default(ci->params, ctx->id("REG_OPCODEIN_1_RST"), "RST0"));
- tg.config.add_enum(dsp + ".REG_OUTPUT0_CLK",
- str_or_default(ci->params, ctx->id("REG_OUTPUT0_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_OUTPUT1_CLK",
- str_or_default(ci->params, ctx->id("REG_OUTPUT1_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".REG_FLAG_CLK", str_or_default(ci->params, ctx->id("REG_FLAG_CLK"), "NONE"));
- tg.config.add_enum(dsp + ".MCPAT_SOURCE", str_or_default(ci->params, ctx->id("MCPAT_SOURCE"), "STATIC"));
- tg.config.add_enum(dsp + ".MASKPAT_SOURCE",
- str_or_default(ci->params, ctx->id("MASKPAT_SOURCE"), "STATIC"));
- tg.config.add_word(dsp + ".MASK01",
- parse_init_str(str_or_default(ci->params, ctx->id("MASK01"), "0x00000000000000"), 56,
- ci->name.c_str(ctx)));
- tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, ctx->id("CLK0_DIV"), "ENABLED"));
- tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, ctx->id("CLK1_DIV"), "ENABLED"));
- tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, ctx->id("CLK2_DIV"), "ENABLED"));
- tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, ctx->id("CLK3_DIV"), "ENABLED"));
- tg.config.add_word(dsp + ".MCPAT",
- parse_init_str(str_or_default(ci->params, ctx->id("MCPAT"), "0x00000000000000"), 56,
- ci->name.c_str(ctx)));
+ str_or_default(ci->params, id_REG_OPCODEOP0_1_RST, "RST0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CLK", str_or_default(ci->params, id_REG_OPCODEIN_0_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CE", str_or_default(ci->params, id_REG_OPCODEIN_0_CE, "CE0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_0_RST", str_or_default(ci->params, id_REG_OPCODEIN_0_RST, "RST0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CLK", str_or_default(ci->params, id_REG_OPCODEIN_1_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_1_CE", str_or_default(ci->params, id_REG_OPCODEIN_1_CE, "CE0"));
+ tg.config.add_enum(dsp + ".REG_OPCODEIN_1_RST", str_or_default(ci->params, id_REG_OPCODEIN_1_RST, "RST0"));
+ tg.config.add_enum(dsp + ".REG_OUTPUT0_CLK", str_or_default(ci->params, id_REG_OUTPUT0_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_OUTPUT1_CLK", str_or_default(ci->params, id_REG_OUTPUT1_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".REG_FLAG_CLK", str_or_default(ci->params, id_REG_FLAG_CLK, "NONE"));
+ tg.config.add_enum(dsp + ".MCPAT_SOURCE", str_or_default(ci->params, id_MCPAT_SOURCE, "STATIC"));
+ tg.config.add_enum(dsp + ".MASKPAT_SOURCE", str_or_default(ci->params, id_MASKPAT_SOURCE, "STATIC"));
+ tg.config.add_word(
+ dsp + ".MASK01",
+ parse_init_str(str_or_default(ci->params, id_MASK01, "0x00000000000000"), 56, ci->name.c_str(ctx)));
+ tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, id_CLK0_DIV, "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, id_CLK1_DIV, "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, id_CLK2_DIV, "ENABLED"));
+ tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, id_CLK3_DIV, "ENABLED"));
+ tg.config.add_word(dsp + ".MCPAT", parse_init_str(str_or_default(ci->params, id_MCPAT, "0x00000000000000"),
+ 56, ci->name.c_str(ctx)));
tg.config.add_word(dsp + ".MASKPAT",
- parse_init_str(str_or_default(ci->params, ctx->id("MASKPAT"), "0x00000000000000"), 56,
- ci->name.c_str(ctx)));
- tg.config.add_word(dsp + ".RNDPAT",
- parse_init_str(str_or_default(ci->params, ctx->id("RNDPAT"), "0x00000000000000"), 56,
+ parse_init_str(str_or_default(ci->params, id_MASKPAT, "0x00000000000000"), 56,
ci->name.c_str(ctx)));
- tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
- tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, ctx->id("RESETMODE"), "SYNC"));
+ tg.config.add_word(
+ dsp + ".RNDPAT",
+ parse_init_str(str_or_default(ci->params, id_RNDPAT, "0x00000000000000"), 56, ci->name.c_str(ctx)));
+ tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
+ tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
tg.config.add_enum(dsp + ".FORCE_ZERO_BARREL_SHIFT",
- str_or_default(ci->params, ctx->id("FORCE_ZERO_BARREL_SHIFT"), "DISABLED"));
- tg.config.add_enum(dsp + ".LEGACY", str_or_default(ci->params, ctx->id("LEGACY"), "DISABLED"));
+ str_or_default(ci->params, id_FORCE_ZERO_BARREL_SHIFT, "DISABLED"));
+ tg.config.add_enum(dsp + ".LEGACY", str_or_default(ci->params, id_LEGACY, "DISABLED"));
tg.config.add_enum(dsp + ".MODE", "ALU54B");
@@ -1332,14 +1298,14 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tg.config.add_enum("DSP_LEFT.CIBOUT", "ON");
else
tg.config.add_enum("DSP_RIGHT.CIBOUT", "ON");
- if (str_or_default(ci->params, ctx->id("REG_FLAG_CLK"), "NONE") == "NONE") {
+ if (str_or_default(ci->params, id_REG_FLAG_CLK, "NONE") == "NONE") {
if (dsp == "ALU54_7") {
tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
} else if (dsp == "ALU54_3") {
tg.config.add_enum("MULT18_5.CIBOUT_BYP", "ON");
}
}
- if (str_or_default(ci->params, ctx->id("REG_OUTPUT0_CLK"), "NONE") == "NONE") {
+ if (str_or_default(ci->params, id_REG_OUTPUT0_CLK, "NONE") == "NONE") {
if (dsp == "ALU54_7") {
tg.config.add_enum("MULT18_4.CIBOUT_BYP", "ON");
} else if (dsp == "ALU54_3") {
@@ -1354,14 +1320,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tg.config.add_enum("MODE", "EHXPLLL");
- tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, ctx->id("CLKI_DIV"), 1) - 1, 7));
- tg.config.add_word("CLKFB_DIV",
- int_to_bitvector(int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1) - 1, 7));
+ tg.config.add_word("CLKI_DIV", int_to_bitvector(int_or_default(ci->params, id_CLKI_DIV, 1) - 1, 7));
+ tg.config.add_word("CLKFB_DIV", int_to_bitvector(int_or_default(ci->params, id_CLKFB_DIV, 1) - 1, 7));
- tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, ctx->id("CLKOP_ENABLE"), "ENABLED"));
- tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, ctx->id("CLKOS_ENABLE"), "ENABLED"));
- tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, ctx->id("CLKOS2_ENABLE"), "ENABLED"));
- tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, ctx->id("CLKOS3_ENABLE"), "ENABLED"));
+ tg.config.add_enum("CLKOP_ENABLE", str_or_default(ci->params, id_CLKOP_ENABLE, "ENABLED"));
+ tg.config.add_enum("CLKOS_ENABLE", str_or_default(ci->params, id_CLKOS_ENABLE, "ENABLED"));
+ tg.config.add_enum("CLKOS2_ENABLE", str_or_default(ci->params, id_CLKOS2_ENABLE, "ENABLED"));
+ tg.config.add_enum("CLKOS3_ENABLE", str_or_default(ci->params, id_CLKOS3_ENABLE, "ENABLED"));
for (std::string out : {"CLKOP", "CLKOS", "CLKOS2", "CLKOS3"}) {
tg.config.add_word(out + "_DIV",
@@ -1372,73 +1337,59 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
int_to_bitvector(int_or_default(ci->params, ctx->id(out + "_FPHASE"), 0), 3));
}
- tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP"));
- tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOP_TRIM_POL"), "RISING"));
+ tg.config.add_enum("FEEDBK_PATH", str_or_default(ci->params, id_FEEDBK_PATH, "CLKOP"));
+ tg.config.add_enum("CLKOP_TRIM_POL", str_or_default(ci->params, id_CLKOP_TRIM_POL, "RISING"));
- tg.config.add_enum("CLKOP_TRIM_DELAY", intstr_or_default(ci->params, ctx->id("CLKOP_TRIM_DELAY"), "0"));
+ tg.config.add_enum("CLKOP_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOP_TRIM_DELAY, "0"));
- tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, ctx->id("CLKOS_TRIM_POL"), "RISING"));
+ tg.config.add_enum("CLKOS_TRIM_POL", str_or_default(ci->params, id_CLKOS_TRIM_POL, "RISING"));
- tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, ctx->id("CLKOS_TRIM_DELAY"), "0"));
+ tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOS_TRIM_DELAY, "0"));
- tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXA"),
+ tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, id_OUTDIVIDER_MUXA,
get_net_or_empty(ci, id_CLKOP) ? "DIVA" : "REFCLK"));
- tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXB"),
+ tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, id_OUTDIVIDER_MUXB,
get_net_or_empty(ci, id_CLKOP) ? "DIVB" : "REFCLK"));
- tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXC"),
+ tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, id_OUTDIVIDER_MUXC,
get_net_or_empty(ci, id_CLKOP) ? "DIVC" : "REFCLK"));
- tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, ctx->id("OUTDIVIDER_MUXD"),
+ tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, id_OUTDIVIDER_MUXD,
get_net_or_empty(ci, id_CLKOP) ? "DIVD" : "REFCLK"));
- tg.config.add_word("PLL_LOCK_MODE",
- int_to_bitvector(int_or_default(ci->params, ctx->id("PLL_LOCK_MODE"), 0), 3));
-
- tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, ctx->id("STDBY_ENABLE"), "DISABLED"));
- tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, ctx->id("REFIN_RESET"), "DISABLED"));
- tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, ctx->id("SYNC_ENABLE"), "DISABLED"));
- tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, ctx->id("INT_LOCK_STICKY"), "ENABLED"));
- tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, ctx->id("DPHASE_SOURCE"), "DISABLED"));
- tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, ctx->id("PLLRST_ENA"), "DISABLED"));
- tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, ctx->id("INTFB_WAKE"), "DISABLED"));
-
- tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, ctx->id("KVCO"), 0), 3));
- tg.config.add_word("LPF_CAPACITOR",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_CAPACITOR"), 0), 2));
- tg.config.add_word("LPF_RESISTOR",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("LPF_RESISTOR"), 0), 7));
- tg.config.add_word("ICP_CURRENT",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("ICP_CURRENT"), 0), 5));
+ tg.config.add_word("PLL_LOCK_MODE", int_to_bitvector(int_or_default(ci->params, id_PLL_LOCK_MODE, 0), 3));
+
+ tg.config.add_enum("STDBY_ENABLE", str_or_default(ci->params, id_STDBY_ENABLE, "DISABLED"));
+ tg.config.add_enum("REFIN_RESET", str_or_default(ci->params, id_REFIN_RESET, "DISABLED"));
+ tg.config.add_enum("SYNC_ENABLE", str_or_default(ci->params, id_SYNC_ENABLE, "DISABLED"));
+ tg.config.add_enum("INT_LOCK_STICKY", str_or_default(ci->params, id_INT_LOCK_STICKY, "ENABLED"));
+ tg.config.add_enum("DPHASE_SOURCE", str_or_default(ci->params, id_DPHASE_SOURCE, "DISABLED"));
+ tg.config.add_enum("PLLRST_ENA", str_or_default(ci->params, id_PLLRST_ENA, "DISABLED"));
+ tg.config.add_enum("INTFB_WAKE", str_or_default(ci->params, id_INTFB_WAKE, "DISABLED"));
+
+ tg.config.add_word("KVCO", int_to_bitvector(int_or_default(ci->attrs, id_KVCO, 0), 3));
+ tg.config.add_word("LPF_CAPACITOR", int_to_bitvector(int_or_default(ci->attrs, id_LPF_CAPACITOR, 0), 2));
+ tg.config.add_word("LPF_RESISTOR", int_to_bitvector(int_or_default(ci->attrs, id_LPF_RESISTOR, 0), 7));
+ tg.config.add_word("ICP_CURRENT", int_to_bitvector(int_or_default(ci->attrs, id_ICP_CURRENT, 0), 5));
tg.config.add_word("FREQ_LOCK_ACCURACY",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("FREQ_LOCK_ACCURACY"), 0), 2));
+ int_to_bitvector(int_or_default(ci->attrs, id_FREQ_LOCK_ACCURACY, 0), 2));
- tg.config.add_word("MFG_GMC_GAIN",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_GAIN"), 0), 3));
- tg.config.add_word("MFG_GMC_TEST",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_TEST"), 14), 4));
- tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG1_TEST"), 0), 3));
- tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG2_TEST"), 0), 3));
+ tg.config.add_word("MFG_GMC_GAIN", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_GAIN, 0), 3));
+ tg.config.add_word("MFG_GMC_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_TEST, 14), 4));
+ tg.config.add_word("MFG1_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG1_TEST, 0), 3));
+ tg.config.add_word("MFG2_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG2_TEST, 0), 3));
tg.config.add_word("MFG_FORCE_VFILTER",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FORCE_VFILTER"), 0), 1));
- tg.config.add_word("MFG_ICP_TEST",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ICP_TEST"), 0), 1));
- tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_EN_UP"), 0), 1));
- tg.config.add_word("MFG_FLOAT_ICP",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_FLOAT_ICP"), 0), 1));
- tg.config.add_word("MFG_GMC_PRESET",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_PRESET"), 0), 1));
- tg.config.add_word("MFG_LF_PRESET",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_PRESET"), 0), 1));
- tg.config.add_word("MFG_GMC_RESET",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMC_RESET"), 0), 1));
- tg.config.add_word("MFG_LF_RESET",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESET"), 0), 1));
- tg.config.add_word("MFG_LF_RESGRND",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_LF_RESGRND"), 0), 1));
- tg.config.add_word("MFG_GMCREF_SEL",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_GMCREF_SEL"), 0), 2));
+ int_to_bitvector(int_or_default(ci->attrs, id_MFG_FORCE_VFILTER, 0), 1));
+ tg.config.add_word("MFG_ICP_TEST", int_to_bitvector(int_or_default(ci->attrs, id_MFG_ICP_TEST, 0), 1));
+ tg.config.add_word("MFG_EN_UP", int_to_bitvector(int_or_default(ci->attrs, id_MFG_EN_UP, 0), 1));
+ tg.config.add_word("MFG_FLOAT_ICP", int_to_bitvector(int_or_default(ci->attrs, id_MFG_FLOAT_ICP, 0), 1));
+ tg.config.add_word("MFG_GMC_PRESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_PRESET, 0), 1));
+ tg.config.add_word("MFG_LF_PRESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_PRESET, 0), 1));
+ tg.config.add_word("MFG_GMC_RESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMC_RESET, 0), 1));
+ tg.config.add_word("MFG_LF_RESET", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_RESET, 0), 1));
+ tg.config.add_word("MFG_LF_RESGRND", int_to_bitvector(int_or_default(ci->attrs, id_MFG_LF_RESGRND, 0), 1));
+ tg.config.add_word("MFG_GMCREF_SEL", int_to_bitvector(int_or_default(ci->attrs, id_MFG_GMCREF_SEL, 0), 2));
tg.config.add_word("MFG_ENABLE_FILTEROPAMP",
- int_to_bitvector(int_or_default(ci->attrs, ctx->id("MFG_ENABLE_FILTEROPAMP"), 0), 1));
+ int_to_bitvector(int_or_default(ci->attrs, id_MFG_ENABLE_FILTEROPAMP, 0), 1));
cc.tilegroups.push_back(tg);
} else if (ci->type == id_IOLOGIC || ci->type == id_SIOLOGIC) {
@@ -1466,23 +1417,22 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
} else if (ci->type == id_EXTREFB) {
TileGroup tg;
tg.tiles = get_dcu_tiles(ctx, ci->bel);
- tg.config.add_word(
- "EXTREF.REFCK_DCBIAS_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("REFCK_DCBIAS_EN"), Property(0)), 1));
+ tg.config.add_word("EXTREF.REFCK_DCBIAS_EN",
+ parse_config_str(get_or_default(ci->params, id_REFCK_DCBIAS_EN, Property(0)), 1));
tg.config.add_word("EXTREF.REFCK_RTERM",
- parse_config_str(get_or_default(ci->params, ctx->id("REFCK_RTERM"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_REFCK_RTERM, Property(0)), 1));
tg.config.add_word("EXTREF.REFCK_PWDNB",
- parse_config_str(get_or_default(ci->params, ctx->id("REFCK_PWDNB"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_REFCK_PWDNB, Property(0)), 1));
cc.tilegroups.push_back(tg);
} else if (ci->type == id_PCSCLKDIV) {
Loc loc = ctx->getBelLocation(ci->bel);
std::string tname = ctx->get_tile_by_type_loc(loc.y + 1, loc.x, "BMID_0H");
cc.tiles[tname].add_enum("PCSCLKDIV" + std::to_string(loc.z),
- str_or_default(ci->params, ctx->id("GSR"), "ENABLED"));
+ str_or_default(ci->params, id_GSR, "ENABLED"));
} else if (ci->type == id_DTR) {
cc.tiles[ctx->get_tile_by_type("DTR")].add_enum("DTR.MODE", "DTR");
} else if (ci->type == id_OSCG) {
- int div = int_or_default(ci->params, ctx->id("DIV"), 128);
+ int div = int_or_default(ci->params, id_DIV, 128);
if (div == 128)
div = 127;
cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("OSC.DIV", std::to_string(div));
@@ -1494,22 +1444,22 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
log_warning("USRMCLK will not function correctly when MASTER_SPI_PORT is set to ENABLE.\n");
cc.tiles[ctx->get_tile_by_type("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK");
} else if (ci->type == id_GSR) {
- cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum(
- "GSR.GSRMODE", str_or_default(ci->params, ctx->id("MODE"), "ACTIVE_LOW"));
- cc.tiles[ctx->get_tile_by_type("VIQ_BUF")].add_enum(
- "GSR.SYNCMODE", str_or_default(ci->params, ctx->id("SYNCMODE"), "ASYNC"));
+ cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("GSR.GSRMODE",
+ str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
+ cc.tiles[ctx->get_tile_by_type("VIQ_BUF")].add_enum("GSR.SYNCMODE",
+ str_or_default(ci->params, id_SYNCMODE, "ASYNC"));
} else if (ci->type == id_JTAGG) {
- cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum(
- "JTAG.ER1", str_or_default(ci->params, ctx->id("ER1"), "ENABLED"));
- cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum(
- "JTAG.ER2", str_or_default(ci->params, ctx->id("ER2"), "ENABLED"));
+ cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER1",
+ str_or_default(ci->params, id_ER1, "ENABLED"));
+ cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER2",
+ str_or_default(ci->params, id_ER2, "ENABLED"));
} else if (ci->type == id_CLKDIVF) {
Loc loc = ctx->getBelLocation(ci->bel);
bool r = loc.x > 5;
std::string clkdiv = std::string("CLKDIV_") + (r ? "R" : "L") + std::to_string(loc.z);
std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
- cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, ctx->id("DIV"), "2.0"));
- cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+ cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, id_DIV, "2.0"));
+ cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
} else if (ci->type == id_TRELLIS_ECLKBUF) {
} else if (ci->type == id_DQSBUFM) {
Loc loc = ctx->getBelLocation(ci->bel);
@@ -1521,13 +1471,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, pic + "0_DQS2"));
tg.tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x, pic + "1_DQS3"));
tg.config.add_enum("DQS.MODE", "DQSBUFM");
- tg.config.add_enum("DQS.DQS_LI_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS"));
- tg.config.add_enum("DQS.DQS_LO_DEL_ADJ", str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS"));
- int li_del_value = int_or_default(ci->params, ctx->id("DQS_LI_DEL_VAL"), 0);
- if (str_or_default(ci->params, ctx->id("DQS_LI_DEL_ADJ"), "PLUS") == "MINUS")
+ tg.config.add_enum("DQS.DQS_LI_DEL_ADJ", str_or_default(ci->params, id_DQS_LI_DEL_ADJ, "PLUS"));
+ tg.config.add_enum("DQS.DQS_LO_DEL_ADJ", str_or_default(ci->params, id_DQS_LO_DEL_ADJ, "PLUS"));
+ int li_del_value = int_or_default(ci->params, id_DQS_LI_DEL_VAL, 0);
+ if (str_or_default(ci->params, id_DQS_LI_DEL_ADJ, "PLUS") == "MINUS")
li_del_value = (256 - li_del_value) & 0xFF;
- int lo_del_value = int_or_default(ci->params, ctx->id("DQS_LO_DEL_VAL"), 0);
- if (str_or_default(ci->params, ctx->id("DQS_LO_DEL_ADJ"), "PLUS") == "MINUS")
+ int lo_del_value = int_or_default(ci->params, id_DQS_LO_DEL_VAL, 0);
+ if (str_or_default(ci->params, id_DQS_LO_DEL_ADJ, "PLUS") == "MINUS")
lo_del_value = (256 - lo_del_value) & 0xFF;
tg.config.add_word("DQS.DQS_LI_DEL_VAL", int_to_bitvector(li_del_value, 8));
tg.config.add_word("DQS.DQS_LO_DEL_VAL", int_to_bitvector(lo_del_value, 8));
@@ -1539,7 +1489,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
? "YES"
: "NO");
tg.config.add_enum("DQS.DDRDEL", get_net_or_empty(ci, id_DDRDEL) != nullptr ? "DDRDEL" : "0");
- tg.config.add_enum("DQS.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
+ tg.config.add_enum("DQS.GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
cc.tilegroups.push_back(tg);
} else if (ci->type == id_ECLKSYNCB) {
Loc loc = ctx->getBelLocation(ci->bel);
@@ -1565,9 +1515,8 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tiletype += "A";
std::string tile = ctx->get_tile_by_type(tiletype);
cc.tiles[tile].add_enum("DDRDLL.MODE", "DDRDLLA");
- cc.tiles[tile].add_enum("DDRDLL.GSR", str_or_default(ci->params, ctx->id("GSR"), "DISABLED"));
- cc.tiles[tile].add_enum("DDRDLL.FORCE_MAX_DELAY",
- str_or_default(ci->params, ctx->id("FORCE_MAX_DELAY"), "NO"));
+ cc.tiles[tile].add_enum("DDRDLL.GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
+ cc.tiles[tile].add_enum("DDRDLL.FORCE_MAX_DELAY", str_or_default(ci->params, id_FORCE_MAX_DELAY, "NO"));
} else {
NPNR_ASSERT_FALSE("unsupported cell type");
}
diff --git a/ecp5/cells.cc b/ecp5/cells.cc
index e5ab4d4b..6d88af75 100644
--- a/ecp5/cells.cc
+++ b/ecp5/cells.cc
@@ -25,12 +25,6 @@
NEXTPNR_NAMESPACE_BEGIN
-void add_port(const Context *ctx, CellInfo *cell, std::string name, PortType dir)
-{
- IdString id = ctx->id(name);
- cell->ports[id] = PortInfo{id, nullptr, dir};
-}
-
std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::string name)
{
static int auto_idx = 0;
@@ -49,133 +43,133 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
}
NPNR_ASSERT(tgt != BelId());
for (auto port : ctx->getBelPins(tgt)) {
- add_port(ctx, new_cell.get(), port.str(ctx), ctx->getBelPinType(tgt, port));
+ new_cell->ports[port] = PortInfo{port, nullptr, ctx->getBelPinType(tgt, port)};
}
};
- if (type == ctx->id("TRELLIS_SLICE")) {
- new_cell->params[ctx->id("MODE")] = std::string("LOGIC");
- new_cell->params[ctx->id("GSR")] = std::string("DISABLED");
- new_cell->params[ctx->id("SRMODE")] = std::string("LSR_OVER_CE");
- new_cell->params[ctx->id("CEMUX")] = std::string("1");
- new_cell->params[ctx->id("CLKMUX")] = std::string("CLK");
- new_cell->params[ctx->id("LSRMUX")] = std::string("LSR");
- new_cell->params[ctx->id("LUT0_INITVAL")] = Property(0, 16);
- new_cell->params[ctx->id("LUT1_INITVAL")] = Property(0, 16);
- new_cell->params[ctx->id("REG0_SD")] = std::string("0");
- new_cell->params[ctx->id("REG1_SD")] = std::string("0");
- new_cell->params[ctx->id("REG0_REGSET")] = std::string("RESET");
- new_cell->params[ctx->id("REG1_REGSET")] = std::string("RESET");
- new_cell->params[ctx->id("CCU2_INJECT1_0")] = std::string("NO");
- new_cell->params[ctx->id("CCU2_INJECT1_1")] = std::string("NO");
- new_cell->params[ctx->id("WREMUX")] = std::string("WRE");
-
- add_port(ctx, new_cell.get(), "A0", PORT_IN);
- add_port(ctx, new_cell.get(), "B0", PORT_IN);
- add_port(ctx, new_cell.get(), "C0", PORT_IN);
- add_port(ctx, new_cell.get(), "D0", PORT_IN);
-
- add_port(ctx, new_cell.get(), "A1", PORT_IN);
- add_port(ctx, new_cell.get(), "B1", PORT_IN);
- add_port(ctx, new_cell.get(), "C1", PORT_IN);
- add_port(ctx, new_cell.get(), "D1", PORT_IN);
-
- add_port(ctx, new_cell.get(), "M0", PORT_IN);
- add_port(ctx, new_cell.get(), "M1", PORT_IN);
-
- add_port(ctx, new_cell.get(), "FCI", PORT_IN);
- add_port(ctx, new_cell.get(), "FXA", PORT_IN);
- add_port(ctx, new_cell.get(), "FXB", PORT_IN);
-
- add_port(ctx, new_cell.get(), "CLK", PORT_IN);
- add_port(ctx, new_cell.get(), "LSR", PORT_IN);
- add_port(ctx, new_cell.get(), "CE", PORT_IN);
-
- add_port(ctx, new_cell.get(), "DI0", PORT_IN);
- add_port(ctx, new_cell.get(), "DI1", PORT_IN);
-
- add_port(ctx, new_cell.get(), "WD0", PORT_IN);
- add_port(ctx, new_cell.get(), "WD1", PORT_IN);
- add_port(ctx, new_cell.get(), "WAD0", PORT_IN);
- add_port(ctx, new_cell.get(), "WAD1", PORT_IN);
- add_port(ctx, new_cell.get(), "WAD2", PORT_IN);
- add_port(ctx, new_cell.get(), "WAD3", PORT_IN);
- add_port(ctx, new_cell.get(), "WRE", PORT_IN);
- add_port(ctx, new_cell.get(), "WCK", PORT_IN);
-
- add_port(ctx, new_cell.get(), "F0", PORT_OUT);
- add_port(ctx, new_cell.get(), "Q0", PORT_OUT);
- add_port(ctx, new_cell.get(), "F1", PORT_OUT);
- add_port(ctx, new_cell.get(), "Q1", PORT_OUT);
-
- add_port(ctx, new_cell.get(), "FCO", PORT_OUT);
- add_port(ctx, new_cell.get(), "OFX0", PORT_OUT);
- add_port(ctx, new_cell.get(), "OFX1", PORT_OUT);
-
- add_port(ctx, new_cell.get(), "WDO0", PORT_OUT);
- add_port(ctx, new_cell.get(), "WDO1", PORT_OUT);
- add_port(ctx, new_cell.get(), "WDO2", PORT_OUT);
- add_port(ctx, new_cell.get(), "WDO3", PORT_OUT);
- add_port(ctx, new_cell.get(), "WADO0", PORT_OUT);
- add_port(ctx, new_cell.get(), "WADO1", PORT_OUT);
- add_port(ctx, new_cell.get(), "WADO2", PORT_OUT);
- add_port(ctx, new_cell.get(), "WADO3", PORT_OUT);
- } else if (type == ctx->id("TRELLIS_IO")) {
- new_cell->params[ctx->id("DIR")] = std::string("INPUT");
- new_cell->attrs[ctx->id("IO_TYPE")] = std::string("LVCMOS33");
- new_cell->params[ctx->id("DATAMUX_ODDR")] = std::string("PADDO");
- new_cell->params[ctx->id("DATAMUX_MDDR")] = std::string("PADDO");
-
- add_port(ctx, new_cell.get(), "B", PORT_INOUT);
- add_port(ctx, new_cell.get(), "I", PORT_IN);
- add_port(ctx, new_cell.get(), "T", PORT_IN);
- add_port(ctx, new_cell.get(), "O", PORT_OUT);
-
- add_port(ctx, new_cell.get(), "IOLDO", PORT_IN);
- add_port(ctx, new_cell.get(), "IOLTO", PORT_IN);
-
- } else if (type == ctx->id("LUT4")) {
- new_cell->params[ctx->id("INIT")] = Property(0, 16);
-
- add_port(ctx, new_cell.get(), "A", PORT_IN);
- add_port(ctx, new_cell.get(), "B", PORT_IN);
- add_port(ctx, new_cell.get(), "C", PORT_IN);
- add_port(ctx, new_cell.get(), "D", PORT_IN);
- add_port(ctx, new_cell.get(), "Z", PORT_OUT);
- } else if (type == ctx->id("CCU2C")) {
- new_cell->params[ctx->id("INIT0")] = Property(0, 16);
- new_cell->params[ctx->id("INIT1")] = Property(0, 16);
- new_cell->params[ctx->id("INJECT1_0")] = std::string("YES");
- new_cell->params[ctx->id("INJECT1_1")] = std::string("YES");
-
- add_port(ctx, new_cell.get(), "CIN", PORT_IN);
-
- add_port(ctx, new_cell.get(), "A0", PORT_IN);
- add_port(ctx, new_cell.get(), "B0", PORT_IN);
- add_port(ctx, new_cell.get(), "C0", PORT_IN);
- add_port(ctx, new_cell.get(), "D0", PORT_IN);
-
- add_port(ctx, new_cell.get(), "A1", PORT_IN);
- add_port(ctx, new_cell.get(), "B1", PORT_IN);
- add_port(ctx, new_cell.get(), "C1", PORT_IN);
- add_port(ctx, new_cell.get(), "D1", PORT_IN);
-
- add_port(ctx, new_cell.get(), "S0", PORT_OUT);
- add_port(ctx, new_cell.get(), "S1", PORT_OUT);
- add_port(ctx, new_cell.get(), "COUT", PORT_OUT);
-
- } else if (type == ctx->id("DCCA")) {
- add_port(ctx, new_cell.get(), "CLKI", PORT_IN);
- add_port(ctx, new_cell.get(), "CLKO", PORT_OUT);
- add_port(ctx, new_cell.get(), "CE", PORT_IN);
+ if (type == id_TRELLIS_SLICE) {
+ new_cell->params[id_MODE] = std::string("LOGIC");
+ new_cell->params[id_GSR] = std::string("DISABLED");
+ new_cell->params[id_SRMODE] = std::string("LSR_OVER_CE");
+ new_cell->params[id_CEMUX] = std::string("1");
+ new_cell->params[id_CLKMUX] = std::string("CLK");
+ new_cell->params[id_LSRMUX] = std::string("LSR");
+ new_cell->params[id_LUT0_INITVAL] = Property(0, 16);
+ new_cell->params[id_LUT1_INITVAL] = Property(0, 16);
+ new_cell->params[id_REG0_SD] = std::string("0");
+ new_cell->params[id_REG1_SD] = std::string("0");
+ new_cell->params[id_REG0_REGSET] = std::string("RESET");
+ new_cell->params[id_REG1_REGSET] = std::string("RESET");
+ new_cell->params[id_CCU2_INJECT1_0] = std::string("NO");
+ new_cell->params[id_CCU2_INJECT1_1] = std::string("NO");
+ new_cell->params[id_WREMUX] = std::string("WRE");
+
+ new_cell->addInput(id_A0);
+ new_cell->addInput(id_B0);
+ new_cell->addInput(id_C0);
+ new_cell->addInput(id_D0);
+
+ new_cell->addInput(id_A1);
+ new_cell->addInput(id_B1);
+ new_cell->addInput(id_C1);
+ new_cell->addInput(id_D1);
+
+ new_cell->addInput(id_M0);
+ new_cell->addInput(id_M1);
+
+ new_cell->addInput(id_FCI);
+ new_cell->addInput(id_FXA);
+ new_cell->addInput(id_FXB);
+
+ new_cell->addInput(id_CLK);
+ new_cell->addInput(id_LSR);
+ new_cell->addInput(id_CE);
+
+ new_cell->addInput(id_DI0);
+ new_cell->addInput(id_DI1);
+
+ new_cell->addInput(id_WD0);
+ new_cell->addInput(id_WD1);
+ new_cell->addInput(id_WAD0);
+ new_cell->addInput(id_WAD1);
+ new_cell->addInput(id_WAD2);
+ new_cell->addInput(id_WAD3);
+ new_cell->addInput(id_WRE);
+ new_cell->addInput(id_WCK);
+
+ new_cell->addOutput(id_F0);
+ new_cell->addOutput(id_Q0);
+ new_cell->addOutput(id_F1);
+ new_cell->addOutput(id_Q1);
+
+ new_cell->addOutput(id_FCO);
+ new_cell->addOutput(id_OFX0);
+ new_cell->addOutput(id_OFX1);
+
+ new_cell->addOutput(id_WDO0);
+ new_cell->addOutput(id_WDO1);
+ new_cell->addOutput(id_WDO2);
+ new_cell->addOutput(id_WDO3);
+ new_cell->addOutput(id_WADO0);
+ new_cell->addOutput(id_WADO1);
+ new_cell->addOutput(id_WADO2);
+ new_cell->addOutput(id_WADO3);
+ } else if (type == id_TRELLIS_IO) {
+ new_cell->params[id_DIR] = std::string("INPUT");
+ new_cell->attrs[id_IO_TYPE] = std::string("LVCMOS33");
+ new_cell->params[id_DATAMUX_ODDR] = std::string("PADDO");
+ new_cell->params[id_DATAMUX_MDDR] = std::string("PADDO");
+
+ new_cell->addInout(id_B);
+ new_cell->addInput(id_I);
+ new_cell->addInput(id_T);
+ new_cell->addOutput(id_O);
+
+ new_cell->addInput(id_IOLDO);
+ new_cell->addInput(id_IOLTO);
+
+ } else if (type == id_LUT4) {
+ new_cell->params[id_INIT] = Property(0, 16);
+
+ new_cell->addInput(id_A);
+ new_cell->addInput(id_B);
+ new_cell->addInput(id_C);
+ new_cell->addInput(id_D);
+ new_cell->addOutput(id_Z);
+ } else if (type == id_CCU2C) {
+ new_cell->params[id_INIT0] = Property(0, 16);
+ new_cell->params[id_INIT1] = Property(0, 16);
+ new_cell->params[id_INJECT1_0] = std::string("YES");
+ new_cell->params[id_INJECT1_1] = std::string("YES");
+
+ new_cell->addInput(id_CIN);
+
+ new_cell->addInput(id_A0);
+ new_cell->addInput(id_B0);
+ new_cell->addInput(id_C0);
+ new_cell->addInput(id_D0);
+
+ new_cell->addInput(id_A1);
+ new_cell->addInput(id_B1);
+ new_cell->addInput(id_C1);
+ new_cell->addInput(id_D1);
+
+ new_cell->addOutput(id_S0);
+ new_cell->addOutput(id_S1);
+ new_cell->addOutput(id_COUT);
+
+ } else if (type == id_DCCA) {
+ new_cell->addInput(id_CLKI);
+ new_cell->addOutput(id_CLKO);
+ new_cell->addInput(id_CE);
} else if (type == id_IOLOGIC || type == id_SIOLOGIC) {
- new_cell->params[ctx->id("MODE")] = std::string("NONE");
- new_cell->params[ctx->id("GSR")] = std::string("DISABLED");
- new_cell->params[ctx->id("CLKIMUX")] = std::string("CLK");
- new_cell->params[ctx->id("CLKOMUX")] = std::string("CLK");
- new_cell->params[ctx->id("LSRIMUX")] = std::string("0");
- new_cell->params[ctx->id("LSROMUX")] = std::string("0");
- new_cell->params[ctx->id("LSRMUX")] = std::string("LSR");
+ new_cell->params[id_MODE] = std::string("NONE");
+ new_cell->params[id_GSR] = std::string("DISABLED");
+ new_cell->params[id_CLKIMUX] = std::string("CLK");
+ new_cell->params[id_CLKOMUX] = std::string("CLK");
+ new_cell->params[id_LSRIMUX] = std::string("0");
+ new_cell->params[id_LSROMUX] = std::string("0");
+ new_cell->params[id_LSRMUX] = std::string("LSR");
new_cell->params[ctx->id("DELAY.OUTDEL")] = std::string("DISABLED");
new_cell->params[ctx->id("DELAY.DEL_VALUE")] = Property(0, 7);
@@ -189,7 +183,7 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
new_cell->params[ctx->id("MODDRX.MODE")] = std::string("NONE");
new_cell->params[ctx->id("MTDDRX.MODE")] = std::string("NONE");
- new_cell->params[ctx->id("IOLTOMUX")] = std::string("NONE");
+ new_cell->params[id_IOLTOMUX] = std::string("NONE");
new_cell->params[ctx->id("MTDDRX.DQSW_INVERT")] = std::string("DISABLED");
new_cell->params[ctx->id("MTDDRX.REGSET")] = std::string("RESET");
@@ -198,8 +192,8 @@ std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::str
// Just copy ports from the Bel
copy_bel_ports();
} else if (type == id_TRELLIS_ECLKBUF) {
- add_port(ctx, new_cell.get(), "ECLKI", PORT_IN);
- add_port(ctx, new_cell.get(), "ECLKO", PORT_OUT);
+ new_cell->addInput(id_ECLKI);
+ new_cell->addOutput(id_ECLKO);
} else {
log_error("unable to create ECP5 cell of type %s", type.c_str(ctx));
}
@@ -231,38 +225,38 @@ void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool drive
{
if (lc->hierpath == IdString())
lc->hierpath = ff->hierpath;
- bool has_ff = lc->ports.at(ctx->id("Q0")).net != nullptr || lc->ports.at(ctx->id("Q1")).net != nullptr;
+ bool has_ff = lc->ports.at(id_Q0).net != nullptr || lc->ports.at(id_Q1).net != nullptr;
std::string reg = "REG" + std::to_string(index);
- set_param_safe(has_ff, lc, ctx->id("SRMODE"), str_or_default(ff->params, ctx->id("SRMODE"), "LSR_OVER_CE"));
- set_param_safe(has_ff, lc, ctx->id("GSR"), str_or_default(ff->params, ctx->id("GSR"), "DISABLED"));
- set_param_safe(has_ff, lc, ctx->id("CEMUX"), str_or_default(ff->params, ctx->id("CEMUX"), "1"));
- set_param_safe(has_ff, lc, ctx->id("LSRMUX"), str_or_default(ff->params, ctx->id("LSRMUX"), "LSR"));
- set_param_safe(has_ff, lc, ctx->id("CLKMUX"), str_or_default(ff->params, ctx->id("CLKMUX"), "CLK"));
+ set_param_safe(has_ff, lc, id_SRMODE, str_or_default(ff->params, id_SRMODE, "LSR_OVER_CE"));
+ set_param_safe(has_ff, lc, id_GSR, str_or_default(ff->params, id_GSR, "DISABLED"));
+ set_param_safe(has_ff, lc, id_CEMUX, str_or_default(ff->params, id_CEMUX, "1"));
+ set_param_safe(has_ff, lc, id_LSRMUX, str_or_default(ff->params, id_LSRMUX, "LSR"));
+ set_param_safe(has_ff, lc, id_CLKMUX, str_or_default(ff->params, id_CLKMUX, "CLK"));
lc->params[ctx->id(reg + "_SD")] = std::string(driven_by_lut ? "1" : "0");
- lc->params[ctx->id(reg + "_REGSET")] = str_or_default(ff->params, ctx->id("REGSET"), "RESET");
- lc->params[ctx->id(reg + "_LSRMODE")] = str_or_default(ff->params, ctx->id("LSRMODE"), "LSR");
- replace_port_safe(has_ff, ff, ctx->id("CLK"), lc, ctx->id("CLK"));
- if (ff->ports.find(ctx->id("LSR")) != ff->ports.end())
- replace_port_safe(has_ff, ff, ctx->id("LSR"), lc, ctx->id("LSR"));
- if (ff->ports.find(ctx->id("CE")) != ff->ports.end())
- replace_port_safe(has_ff, ff, ctx->id("CE"), lc, ctx->id("CE"));
-
- replace_port(ff, ctx->id("Q"), lc, ctx->id("Q" + std::to_string(index)));
- if (get_net_or_empty(ff, ctx->id("M")) != nullptr) {
+ lc->params[ctx->id(reg + "_REGSET")] = str_or_default(ff->params, id_REGSET, "RESET");
+ lc->params[ctx->id(reg + "_LSRMODE")] = str_or_default(ff->params, id_LSRMODE, "LSR");
+ replace_port_safe(has_ff, ff, id_CLK, lc, id_CLK);
+ if (ff->ports.find(id_LSR) != ff->ports.end())
+ replace_port_safe(has_ff, ff, id_LSR, lc, id_LSR);
+ if (ff->ports.find(id_CE) != ff->ports.end())
+ replace_port_safe(has_ff, ff, id_CE, lc, id_CE);
+
+ replace_port(ff, id_Q, lc, ctx->id("Q" + std::to_string(index)));
+ if (get_net_or_empty(ff, id_M) != nullptr) {
// PRLD FFs that use both M and DI
NPNR_ASSERT(!driven_by_lut);
// As M is used; must route DI through a new LUT
lc->params[ctx->id(reg + "_SD")] = std::string("1");
lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] = Property(0xFF00, 16);
- replace_port(ff, ctx->id("DI"), lc, ctx->id("D" + std::to_string(index)));
- replace_port(ff, ctx->id("M"), lc, ctx->id("M" + std::to_string(index)));
+ replace_port(ff, id_DI, lc, ctx->id("D" + std::to_string(index)));
+ replace_port(ff, id_M, lc, ctx->id("M" + std::to_string(index)));
connect_ports(ctx, lc, ctx->id("F" + std::to_string(index)), lc, ctx->id("DI" + std::to_string(index)));
} else {
if (driven_by_lut) {
- replace_port(ff, ctx->id("DI"), lc, ctx->id("DI" + std::to_string(index)));
+ replace_port(ff, id_DI, lc, ctx->id("DI" + std::to_string(index)));
} else {
- replace_port(ff, ctx->id("DI"), lc, ctx->id("M" + std::to_string(index)));
+ replace_port(ff, id_DI, lc, ctx->id("M" + std::to_string(index)));
}
}
}
@@ -272,62 +266,62 @@ void lut_to_slice(Context *ctx, CellInfo *lut, CellInfo *lc, int index)
if (lc->hierpath == IdString())
lc->hierpath = lut->hierpath;
lc->params[ctx->id("LUT" + std::to_string(index) + "_INITVAL")] =
- get_or_default(lut->params, ctx->id("INIT"), Property(0, 16));
- replace_port(lut, ctx->id("A"), lc, ctx->id("A" + std::to_string(index)));
- replace_port(lut, ctx->id("B"), lc, ctx->id("B" + std::to_string(index)));
- replace_port(lut, ctx->id("C"), lc, ctx->id("C" + std::to_string(index)));
- replace_port(lut, ctx->id("D"), lc, ctx->id("D" + std::to_string(index)));
- replace_port(lut, ctx->id("Z"), lc, ctx->id("F" + std::to_string(index)));
+ get_or_default(lut->params, id_INIT, Property(0, 16));
+ replace_port(lut, id_A, lc, ctx->id("A" + std::to_string(index)));
+ replace_port(lut, id_B, lc, ctx->id("B" + std::to_string(index)));
+ replace_port(lut, id_C, lc, ctx->id("C" + std::to_string(index)));
+ replace_port(lut, id_D, lc, ctx->id("D" + std::to_string(index)));
+ replace_port(lut, id_Z, lc, ctx->id("F" + std::to_string(index)));
}
void ccu2c_to_slice(Context *ctx, CellInfo *ccu, CellInfo *lc)
{
if (lc->hierpath == IdString())
lc->hierpath = ccu->hierpath;
- lc->params[ctx->id("MODE")] = std::string("CCU2");
- lc->params[ctx->id("LUT0_INITVAL")] = get_or_default(ccu->params, ctx->id("INIT0"), Property(0, 16));
- lc->params[ctx->id("LUT1_INITVAL")] = get_or_default(ccu->params, ctx->id("INIT1"), Property(0, 16));
+ lc->params[id_MODE] = std::string("CCU2");
+ lc->params[id_LUT0_INITVAL] = get_or_default(ccu->params, id_INIT0, Property(0, 16));
+ lc->params[id_LUT1_INITVAL] = get_or_default(ccu->params, id_INIT1, Property(0, 16));
- lc->params[ctx->id("CCU2_INJECT1_0")] = str_or_default(ccu->params, ctx->id("INJECT1_0"), "YES");
- lc->params[ctx->id("CCU2_INJECT1_1")] = str_or_default(ccu->params, ctx->id("INJECT1_1"), "YES");
+ lc->params[id_CCU2_INJECT1_0] = str_or_default(ccu->params, id_INJECT1_0, "YES");
+ lc->params[id_CCU2_INJECT1_1] = str_or_default(ccu->params, id_INJECT1_1, "YES");
- replace_port(ccu, ctx->id("CIN"), lc, ctx->id("FCI"));
+ replace_port(ccu, id_CIN, lc, id_FCI);
- replace_port(ccu, ctx->id("A0"), lc, ctx->id("A0"));
- replace_port(ccu, ctx->id("B0"), lc, ctx->id("B0"));
- replace_port(ccu, ctx->id("C0"), lc, ctx->id("C0"));
- replace_port(ccu, ctx->id("D0"), lc, ctx->id("D0"));
+ replace_port(ccu, id_A0, lc, id_A0);
+ replace_port(ccu, id_B0, lc, id_B0);
+ replace_port(ccu, id_C0, lc, id_C0);
+ replace_port(ccu, id_D0, lc, id_D0);
- replace_port(ccu, ctx->id("A1"), lc, ctx->id("A1"));
- replace_port(ccu, ctx->id("B1"), lc, ctx->id("B1"));
- replace_port(ccu, ctx->id("C1"), lc, ctx->id("C1"));
- replace_port(ccu, ctx->id("D1"), lc, ctx->id("D1"));
+ replace_port(ccu, id_A1, lc, id_A1);
+ replace_port(ccu, id_B1, lc, id_B1);
+ replace_port(ccu, id_C1, lc, id_C1);
+ replace_port(ccu, id_D1, lc, id_D1);
- replace_port(ccu, ctx->id("S0"), lc, ctx->id("F0"));
- replace_port(ccu, ctx->id("S1"), lc, ctx->id("F1"));
+ replace_port(ccu, id_S0, lc, id_F0);
+ replace_port(ccu, id_S1, lc, id_F1);
- replace_port(ccu, ctx->id("COUT"), lc, ctx->id("FCO"));
+ replace_port(ccu, id_COUT, lc, id_FCO);
}
void dram_to_ramw(Context *ctx, CellInfo *ram, CellInfo *lc)
{
if (lc->hierpath == IdString())
lc->hierpath = ram->hierpath;
- lc->params[ctx->id("MODE")] = std::string("RAMW");
- replace_port(ram, ctx->id("WAD[0]"), lc, ctx->id("D0"));
- replace_port(ram, ctx->id("WAD[1]"), lc, ctx->id("B0"));
- replace_port(ram, ctx->id("WAD[2]"), lc, ctx->id("C0"));
- replace_port(ram, ctx->id("WAD[3]"), lc, ctx->id("A0"));
-
- replace_port(ram, ctx->id("DI[0]"), lc, ctx->id("C1"));
- replace_port(ram, ctx->id("DI[1]"), lc, ctx->id("A1"));
- replace_port(ram, ctx->id("DI[2]"), lc, ctx->id("D1"));
- replace_port(ram, ctx->id("DI[3]"), lc, ctx->id("B1"));
+ lc->params[id_MODE] = std::string("RAMW");
+ replace_port(ram, ctx->id("WAD[0]"), lc, id_D0);
+ replace_port(ram, ctx->id("WAD[1]"), lc, id_B0);
+ replace_port(ram, ctx->id("WAD[2]"), lc, id_C0);
+ replace_port(ram, ctx->id("WAD[3]"), lc, id_A0);
+
+ replace_port(ram, ctx->id("DI[0]"), lc, id_C1);
+ replace_port(ram, ctx->id("DI[1]"), lc, id_A1);
+ replace_port(ram, ctx->id("DI[2]"), lc, id_D1);
+ replace_port(ram, ctx->id("DI[3]"), lc, id_B1);
}
static unsigned get_dram_init(const Context *ctx, const CellInfo *ram, int bit)
{
- auto init_prop = get_or_default(ram->params, ctx->id("INITVAL"), Property(0, 64));
+ auto init_prop = get_or_default(ram->params, id_INITVAL, Property(0, 64));
NPNR_ASSERT(!init_prop.is_string);
const std::string &idata = init_prop.str;
NPNR_ASSERT(idata.length() == 64);
@@ -346,9 +340,9 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
{
if (lc->hierpath == IdString())
lc->hierpath = ram->hierpath;
- lc->params[ctx->id("MODE")] = std::string("DPRAM");
- lc->params[ctx->id("WREMUX")] = str_or_default(ram->params, ctx->id("WREMUX"), "WRE");
- lc->params[ctx->id("WCKMUX")] = str_or_default(ram->params, ctx->id("WCKMUX"), "WCK");
+ lc->params[id_MODE] = std::string("DPRAM");
+ lc->params[id_WREMUX] = str_or_default(ram->params, id_WREMUX, "WRE");
+ lc->params[id_WCKMUX] = str_or_default(ram->params, id_WCKMUX, "WCK");
unsigned permuted_init0 = 0, permuted_init1 = 0;
unsigned init0 = get_dram_init(ctx, ram, index * 2), init1 = get_dram_init(ctx, ram, index * 2 + 1);
@@ -369,30 +363,30 @@ void dram_to_ram_slice(Context *ctx, CellInfo *ram, CellInfo *lc, CellInfo *ramw
permuted_init1 |= (1 << i);
}
- lc->params[ctx->id("LUT0_INITVAL")] = Property(permuted_init0, 16);
- lc->params[ctx->id("LUT1_INITVAL")] = Property(permuted_init1, 16);
+ lc->params[id_LUT0_INITVAL] = Property(permuted_init0, 16);
+ lc->params[id_LUT1_INITVAL] = Property(permuted_init1, 16);
if (ram->ports.count(ctx->id("RAD[0]"))) {
- connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, ctx->id("D0"));
- connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, ctx->id("D1"));
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, id_D0);
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[0]")).net, lc, id_D1);
}
if (ram->ports.count(ctx->id("RAD[1]"))) {
- connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, ctx->id("B0"));
- connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, ctx->id("B1"));
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, id_B0);
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[1]")).net, lc, id_B1);
}
if (ram->ports.count(ctx->id("RAD[2]"))) {
- connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, ctx->id("C0"));
- connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, ctx->id("C1"));
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, id_C0);
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[2]")).net, lc, id_C1);
}
if (ram->ports.count(ctx->id("RAD[3]"))) {
- connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, ctx->id("A0"));
- connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, ctx->id("A1"));
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, id_A0);
+ connect_port(ctx, ram->ports.at(ctx->id("RAD[3]")).net, lc, id_A1);
}
- if (ram->ports.count(ctx->id("WRE")))
- connect_port(ctx, ram->ports.at(ctx->id("WRE")).net, lc, ctx->id("WRE"));
- if (ram->ports.count(ctx->id("WCK")))
- connect_port(ctx, ram->ports.at(ctx->id("WCK")).net, lc, ctx->id("WCK"));
+ if (ram->ports.count(id_WRE))
+ connect_port(ctx, ram->ports.at(id_WRE).net, lc, id_WRE);
+ if (ram->ports.count(id_WCK))
+ connect_port(ctx, ram->ports.at(id_WCK).net, lc, id_WCK);
connect_ports(ctx, ramw, id_WADO0, lc, id_WAD0);
connect_ports(ctx, ramw, id_WADO1, lc, id_WAD1);
@@ -421,26 +415,26 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
pool<IdString> &todelete_cells)
{
if (nxio->type == ctx->id("$nextpnr_ibuf")) {
- trio->params[ctx->id("DIR")] = std::string("INPUT");
- replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
+ trio->params[id_DIR] = std::string("INPUT");
+ replace_port(nxio, id_O, trio, id_O);
} else if (nxio->type == ctx->id("$nextpnr_obuf")) {
- trio->params[ctx->id("DIR")] = std::string("OUTPUT");
- replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
+ trio->params[id_DIR] = std::string("OUTPUT");
+ replace_port(nxio, id_I, trio, id_I);
} else if (nxio->type == ctx->id("$nextpnr_iobuf")) {
// N.B. tristate will be dealt with below
- NetInfo *i = get_net_or_empty(nxio, ctx->id("I"));
+ NetInfo *i = get_net_or_empty(nxio, id_I);
if (i == nullptr || i->driver.cell == nullptr)
- trio->params[ctx->id("DIR")] = std::string("INPUT");
+ trio->params[id_DIR] = std::string("INPUT");
else {
log_info("%s: %s.%s\n", ctx->nameOf(i), ctx->nameOf(i->driver.cell), ctx->nameOf(i->driver.port));
- trio->params[ctx->id("DIR")] = std::string("BIDIR");
+ trio->params[id_DIR] = std::string("BIDIR");
}
- replace_port(nxio, ctx->id("I"), trio, ctx->id("I"));
- replace_port(nxio, ctx->id("O"), trio, ctx->id("O"));
+ replace_port(nxio, id_I, trio, id_I);
+ replace_port(nxio, id_O, trio, id_O);
} else {
NPNR_ASSERT(false);
}
- NetInfo *donet = trio->ports.at(ctx->id("I")).net, *dinet = trio->ports.at(ctx->id("O")).net;
+ NetInfo *donet = trio->ports.at(id_I).net, *dinet = trio->ports.at(id_O).net;
// Rename I/O nets to avoid conflicts
if (donet != nullptr && donet->name == nxio->name)
@@ -464,20 +458,20 @@ void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::u
ctx->net_aliases.erase(tn_netname);
NetInfo *toplevel_net = ctx->createNet(tn_netname);
toplevel_net->name = tn_netname;
- connect_port(ctx, toplevel_net, trio, ctx->id("B"));
+ connect_port(ctx, toplevel_net, trio, id_B);
ctx->ports[nxio->name].net = toplevel_net;
}
CellInfo *tbuf = net_driven_by(
ctx, donet, [](const Context *ctx, const CellInfo *cell) { return cell->type == ctx->id("$_TBUF_"); },
- ctx->id("Y"));
+ id_Y);
if (tbuf) {
- replace_port(tbuf, ctx->id("A"), trio, ctx->id("I"));
+ replace_port(tbuf, id_A, trio, id_I);
// Need to invert E to form T
- std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, ctx->id("LUT4"), trio->name.str(ctx) + "$invert_T");
- replace_port(tbuf, ctx->id("E"), inv_lut.get(), ctx->id("A"));
- inv_lut->params[ctx->id("INIT")] = Property(21845, 16);
- connect_ports(ctx, inv_lut.get(), ctx->id("Z"), trio, ctx->id("T"));
+ std::unique_ptr<CellInfo> inv_lut = create_ecp5_cell(ctx, id_LUT4, trio->name.str(ctx) + "$invert_T");
+ replace_port(tbuf, id_E, inv_lut.get(), id_A);
+ inv_lut->params[id_INIT] = Property(21845, 16);
+ connect_ports(ctx, inv_lut.get(), id_Z, trio, id_T);
created_cells.push_back(std::move(inv_lut));
if (donet->users.size() > 1) {
diff --git a/ecp5/cells.h b/ecp5/cells.h
index c1165ddc..8f0a8cbf 100644
--- a/ecp5/cells.h
+++ b/ecp5/cells.h
@@ -30,37 +30,36 @@ NEXTPNR_NAMESPACE_BEGIN
std::unique_ptr<CellInfo> create_ecp5_cell(Context *ctx, IdString type, std::string name = "");
// Return true if a cell is a LUT
-inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("LUT4"); }
+inline bool is_lut(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_LUT4; }
// Return true if a cell is a flipflop
-inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("TRELLIS_FF"); }
+inline bool is_ff(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_FF; }
-inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("CCU2C"); }
+inline bool is_carry(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_CCU2C; }
-inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("TRELLIS_SLICE"); }
+inline bool is_lc(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_SLICE; }
-inline bool is_trellis_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("TRELLIS_IO"); }
+inline bool is_trellis_io(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_IO; }
-inline bool is_dpram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("TRELLIS_DPR16X4"); }
+inline bool is_dpram(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_TRELLIS_DPR16X4; }
-inline bool is_pfumx(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("PFUMX"); }
+inline bool is_pfumx(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_PFUMX; }
-inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == ctx->id("L6MUX21"); }
+inline bool is_l6mux(const BaseCtx *ctx, const CellInfo *cell) { return cell->type == id_L6MUX21; }
inline bool is_iologic_input_cell(const BaseCtx *ctx, const CellInfo *cell)
{
- return cell->type == ctx->id("IDDRX1F") || cell->type == ctx->id("IDDRX2F") || cell->type == ctx->id("IDDR71B") ||
- cell->type == ctx->id("IDDRX2DQA") ||
- (cell->type == ctx->id("TRELLIS_FF") && bool_or_default(cell->attrs, ctx->id("syn_useioff")) &&
- (str_or_default(cell->attrs, ctx->id("ioff_dir"), "") != "output"));
+ return cell->type == id_IDDRX1F || cell->type == id_IDDRX2F || cell->type == id_IDDR71B ||
+ cell->type == id_IDDRX2DQA ||
+ (cell->type == id_TRELLIS_FF && bool_or_default(cell->attrs, id_syn_useioff) &&
+ (str_or_default(cell->attrs, id_ioff_dir, "") != "output"));
}
inline bool is_iologic_output_cell(const BaseCtx *ctx, const CellInfo *cell)
{
- return cell->type == ctx->id("ODDRX1F") || cell->type == ctx->id("ODDRX2F") || cell->type == ctx->id("ODDR71B") ||
- cell->type == ctx->id("ODDRX2DQA") || cell->type == ctx->id("ODDRX2DQSB") ||
- cell->type == ctx->id("OSHX2A") ||
- (cell->type == ctx->id("TRELLIS_FF") && bool_or_default(cell->attrs, ctx->id("syn_useioff")) &&
- (str_or_default(cell->attrs, ctx->id("ioff_dir"), "") != "input"));
+ return cell->type == id_ODDRX1F || cell->type == id_ODDRX2F || cell->type == id_ODDR71B ||
+ cell->type == id_ODDRX2DQA || cell->type == id_ODDRX2DQSB || cell->type == id_OSHX2A ||
+ (cell->type == id_TRELLIS_FF && bool_or_default(cell->attrs, id_syn_useioff) &&
+ (str_or_default(cell->attrs, id_ioff_dir, "") != "input"));
}
void ff_to_slice(Context *ctx, CellInfo *ff, CellInfo *lc, int index, bool driven_by_lut);
diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index 335f822a..760e1623 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -1341,3 +1341,513 @@ X(IOLOGIC_MODE_TSREG)
X(DCSC)
X(DCSOUT)
X(MODESEL)
+
+X(ALUT)
+X(ASYNC_RESET_RELEASE)
+X(BEL)
+X(BLUT)
+X(C)
+X(CCU2C)
+X(CCU2_INJECT1_0)
+X(CCU2_INJECT1_1)
+X(CEAMUX)
+X(CEBMUX)
+X(CEIMUX)
+X(CEMUX)
+X(CEOMUX)
+X(CER)
+X(CEW)
+X(CH0_AUTO_CALIB_EN)
+X(CH0_AUTO_FACQ_EN)
+X(CH0_BAND_THRESHOLD)
+X(CH0_CALIB_CK_MODE)
+X(CH0_CC_MATCH_1)
+X(CH0_CC_MATCH_2)
+X(CH0_CC_MATCH_3)
+X(CH0_CC_MATCH_4)
+X(CH0_CDR_CNT4SEL)
+X(CH0_CDR_CNT8SEL)
+X(CH0_CTC_BYPASS)
+X(CH0_DCOATDCFG)
+X(CH0_DCOATDDLY)
+X(CH0_DCOBYPSATD)
+X(CH0_DCOCALDIV)
+X(CH0_DCOCTLGI)
+X(CH0_DCODISBDAVOID)
+X(CH0_DCOFLTDAC)
+X(CH0_DCOFTNRG)
+X(CH0_DCOIOSTUNE)
+X(CH0_DCOITUNE)
+X(CH0_DCOITUNE4LSB)
+X(CH0_DCOIUPDNX2)
+X(CH0_DCONUOFLSB)
+X(CH0_DCOSCALEI)
+X(CH0_DCOSTARTVAL)
+X(CH0_DCOSTEP)
+X(CH0_DEC_BYPASS)
+X(CH0_ENABLE_CG_ALIGN)
+X(CH0_ENC_BYPASS)
+X(CH0_FF_RX_F_CLK_DIS)
+X(CH0_FF_RX_H_CLK_EN)
+X(CH0_FF_TX_F_CLK_DIS)
+X(CH0_FF_TX_H_CLK_EN)
+X(CH0_GE_AN_ENABLE)
+X(CH0_INVERT_RX)
+X(CH0_INVERT_TX)
+X(CH0_LDR_CORE2TX_SEL)
+X(CH0_LDR_RX2CORE_SEL)
+X(CH0_LEQ_OFFSET_SEL)
+X(CH0_LEQ_OFFSET_TRIM)
+X(CH0_LSM_DISABLE)
+X(CH0_MATCH_2_ENABLE)
+X(CH0_MATCH_4_ENABLE)
+X(CH0_MIN_IPG_CNT)
+X(CH0_PCIE_EI_EN)
+X(CH0_PCIE_MODE)
+X(CH0_PCS_DET_TIME_SEL)
+X(CH0_PDEN_SEL)
+X(CH0_PRBS_ENABLE)
+X(CH0_PRBS_LOCK)
+X(CH0_PRBS_SELECTION)
+X(CH0_RATE_MODE_RX)
+X(CH0_RATE_MODE_TX)
+X(CH0_RCV_DCC_EN)
+X(CH0_REG_BAND_OFFSET)
+X(CH0_REG_BAND_SEL)
+X(CH0_REG_IDAC_EN)
+X(CH0_REG_IDAC_SEL)
+X(CH0_REQ_EN)
+X(CH0_REQ_LVL_SET)
+X(CH0_RIO_MODE)
+X(CH0_RLOS_SEL)
+X(CH0_RPWDNB)
+X(CH0_RTERM_RX)
+X(CH0_RTERM_TX)
+X(CH0_RXIN_CM)
+X(CH0_RXTERM_CM)
+X(CH0_RX_DCO_CK_DIV)
+X(CH0_RX_DIV11_SEL)
+X(CH0_RX_GEAR_BYPASS)
+X(CH0_RX_GEAR_MODE)
+X(CH0_RX_LOS_CEQ)
+X(CH0_RX_LOS_EN)
+X(CH0_RX_LOS_HYST_EN)
+X(CH0_RX_LOS_LVL)
+X(CH0_RX_RATE_SEL)
+X(CH0_RX_SB_BYPASS)
+X(CH0_SB_BYPASS)
+X(CH0_SEL_SD_RX_CLK)
+X(CH0_TDRV_DAT_SEL)
+X(CH0_TDRV_POST_EN)
+X(CH0_TDRV_PRE_EN)
+X(CH0_TDRV_SLICE0_CUR)
+X(CH0_TDRV_SLICE0_SEL)
+X(CH0_TDRV_SLICE1_CUR)
+X(CH0_TDRV_SLICE1_SEL)
+X(CH0_TDRV_SLICE2_CUR)
+X(CH0_TDRV_SLICE2_SEL)
+X(CH0_TDRV_SLICE3_CUR)
+X(CH0_TDRV_SLICE3_SEL)
+X(CH0_TDRV_SLICE4_CUR)
+X(CH0_TDRV_SLICE4_SEL)
+X(CH0_TDRV_SLICE5_CUR)
+X(CH0_TDRV_SLICE5_SEL)
+X(CH0_TPWDNB)
+X(CH0_TX_CM_SEL)
+X(CH0_TX_DIV11_SEL)
+X(CH0_TX_GEAR_BYPASS)
+X(CH0_TX_GEAR_MODE)
+X(CH0_TX_POST_SIGN)
+X(CH0_TX_PRE_SIGN)
+X(CH0_UC_MODE)
+X(CH0_UDF_COMMA_A)
+X(CH0_UDF_COMMA_B)
+X(CH0_UDF_COMMA_MASK)
+X(CH0_WA_BYPASS)
+X(CH0_WA_MODE)
+X(CH1_AUTO_CALIB_EN)
+X(CH1_AUTO_FACQ_EN)
+X(CH1_BAND_THRESHOLD)
+X(CH1_CALIB_CK_MODE)
+X(CH1_CC_MATCH_1)
+X(CH1_CC_MATCH_2)
+X(CH1_CC_MATCH_3)
+X(CH1_CC_MATCH_4)
+X(CH1_CDR_CNT4SEL)
+X(CH1_CDR_CNT8SEL)
+X(CH1_CTC_BYPASS)
+X(CH1_DCOATDCFG)
+X(CH1_DCOATDDLY)
+X(CH1_DCOBYPSATD)
+X(CH1_DCOCALDIV)
+X(CH1_DCOCTLGI)
+X(CH1_DCODISBDAVOID)
+X(CH1_DCOFLTDAC)
+X(CH1_DCOFTNRG)
+X(CH1_DCOIOSTUNE)
+X(CH1_DCOITUNE)
+X(CH1_DCOITUNE4LSB)
+X(CH1_DCOIUPDNX2)
+X(CH1_DCONUOFLSB)
+X(CH1_DCOSCALEI)
+X(CH1_DCOSTARTVAL)
+X(CH1_DCOSTEP)
+X(CH1_DEC_BYPASS)
+X(CH1_ENABLE_CG_ALIGN)
+X(CH1_ENC_BYPASS)
+X(CH1_FF_RX_F_CLK_DIS)
+X(CH1_FF_RX_H_CLK_EN)
+X(CH1_FF_TX_F_CLK_DIS)
+X(CH1_FF_TX_H_CLK_EN)
+X(CH1_GE_AN_ENABLE)
+X(CH1_INVERT_RX)
+X(CH1_INVERT_TX)
+X(CH1_LDR_CORE2TX_SEL)
+X(CH1_LDR_RX2CORE_SEL)
+X(CH1_LEQ_OFFSET_SEL)
+X(CH1_LEQ_OFFSET_TRIM)
+X(CH1_LSM_DISABLE)
+X(CH1_MATCH_2_ENABLE)
+X(CH1_MATCH_4_ENABLE)
+X(CH1_MIN_IPG_CNT)
+X(CH1_PCIE_EI_EN)
+X(CH1_PCIE_MODE)
+X(CH1_PCS_DET_TIME_SEL)
+X(CH1_PDEN_SEL)
+X(CH1_PRBS_ENABLE)
+X(CH1_PRBS_LOCK)
+X(CH1_PRBS_SELECTION)
+X(CH1_RATE_MODE_RX)
+X(CH1_RATE_MODE_TX)
+X(CH1_RCV_DCC_EN)
+X(CH1_REG_BAND_OFFSET)
+X(CH1_REG_BAND_SEL)
+X(CH1_REG_IDAC_EN)
+X(CH1_REG_IDAC_SEL)
+X(CH1_REQ_EN)
+X(CH1_REQ_LVL_SET)
+X(CH1_RIO_MODE)
+X(CH1_RLOS_SEL)
+X(CH1_RPWDNB)
+X(CH1_RTERM_RX)
+X(CH1_RTERM_TX)
+X(CH1_RXIN_CM)
+X(CH1_RXTERM_CM)
+X(CH1_RX_DCO_CK_DIV)
+X(CH1_RX_DIV11_SEL)
+X(CH1_RX_GEAR_BYPASS)
+X(CH1_RX_GEAR_MODE)
+X(CH1_RX_LOS_CEQ)
+X(CH1_RX_LOS_EN)
+X(CH1_RX_LOS_HYST_EN)
+X(CH1_RX_LOS_LVL)
+X(CH1_RX_RATE_SEL)
+X(CH1_RX_SB_BYPASS)
+X(CH1_SB_BYPASS)
+X(CH1_SEL_SD_RX_CLK)
+X(CH1_TDRV_DAT_SEL)
+X(CH1_TDRV_POST_EN)
+X(CH1_TDRV_PRE_EN)
+X(CH1_TDRV_SLICE0_CUR)
+X(CH1_TDRV_SLICE0_SEL)
+X(CH1_TDRV_SLICE1_CUR)
+X(CH1_TDRV_SLICE1_SEL)
+X(CH1_TDRV_SLICE2_CUR)
+X(CH1_TDRV_SLICE2_SEL)
+X(CH1_TDRV_SLICE3_CUR)
+X(CH1_TDRV_SLICE3_SEL)
+X(CH1_TDRV_SLICE4_CUR)
+X(CH1_TDRV_SLICE4_SEL)
+X(CH1_TDRV_SLICE5_CUR)
+X(CH1_TDRV_SLICE5_SEL)
+X(CH1_TPWDNB)
+X(CH1_TX_CM_SEL)
+X(CH1_TX_DIV11_SEL)
+X(CH1_TX_GEAR_BYPASS)
+X(CH1_TX_GEAR_MODE)
+X(CH1_TX_POST_SIGN)
+X(CH1_TX_PRE_SIGN)
+X(CH1_UC_MODE)
+X(CH1_UDF_COMMA_A)
+X(CH1_UDF_COMMA_B)
+X(CH1_UDF_COMMA_MASK)
+X(CH1_WA_BYPASS)
+X(CH1_WA_MODE)
+X(CIN)
+X(CLAMP)
+X(CLK0_DIV)
+X(CLK1_DIV)
+X(CLK2_DIV)
+X(CLK3_DIV)
+X(CLKAMUX)
+X(CLKBMUX)
+X(CLKFB_DIV)
+X(CLKIMUX)
+X(CLKI_DIV)
+X(CLKOMUX)
+X(CLKOP_DIV)
+X(CLKOP_ENABLE)
+X(CLKOP_TRIM_DELAY)
+X(CLKOP_TRIM_POL)
+X(CLKOS2_DIV)
+X(CLKOS2_ENABLE)
+X(CLKOS3_DIV)
+X(CLKOS3_ENABLE)
+X(CLKOS_DIV)
+X(CLKOS_ENABLE)
+X(CLKOS_TRIM_DELAY)
+X(CLKOS_TRIM_POL)
+X(CLKR)
+X(CLKW)
+X(COUT)
+X(CSDECODE_A)
+X(CSDECODE_B)
+X(D)
+X(D2)
+X(D3)
+X(D4)
+X(D5)
+X(D6)
+X(DATAMUX_MDDR)
+X(DATAMUX_ODDR)
+X(DATAMUX_OREG)
+X(DATA_WIDTH_A)
+X(DATA_WIDTH_B)
+X(DATA_WIDTH_W)
+X(DCSMODE)
+X(DDRDLLA)
+X(DELAYF)
+X(DELAYG)
+X(DEL_MODE)
+X(DEL_VALUE)
+X(DIFFRESISTOR)
+X(DIR)
+X(DIV)
+X(DPHASE_SOURCE)
+X(DQS_LI_DEL_ADJ)
+X(DQS_LI_DEL_VAL)
+X(DQS_LO_DEL_ADJ)
+X(DQS_LO_DEL_VAL)
+X(DRIVE)
+X(D_BITCLK_FROM_ND_EN)
+X(D_BITCLK_LOCAL_EN)
+X(D_BITCLK_ND_EN)
+X(D_BUS8BIT_SEL)
+X(D_CDR_LOL_SET)
+X(D_CMUSETBIASI)
+X(D_CMUSETI4CPP)
+X(D_CMUSETI4CPZ)
+X(D_CMUSETI4VCO)
+X(D_CMUSETICP4P)
+X(D_CMUSETICP4Z)
+X(D_CMUSETINITVCT)
+X(D_CMUSETISCL4VCO)
+X(D_CMUSETP1GM)
+X(D_CMUSETP2AGM)
+X(D_CMUSETZGM)
+X(D_DCO_CALIB_TIME_SEL)
+X(D_HIGH_MARK)
+X(D_IB_PWDNB)
+X(D_ISETLOS)
+X(D_LOW_MARK)
+X(D_MACROPDB)
+X(D_PD_ISET)
+X(D_PLL_LOL_SET)
+X(D_REFCK_MODE)
+X(D_REQ_ISET)
+X(D_RG_EN)
+X(D_RG_SET)
+X(D_SETICONST_AUX)
+X(D_SETICONST_CH)
+X(D_SETIRPOLY_AUX)
+X(D_SETIRPOLY_CH)
+X(D_SETPLLRC)
+X(D_SYNC_LOCAL_EN)
+X(D_SYNC_ND_EN)
+X(D_TXPLL_PWDNB)
+X(D_TX_VCO_CK_DIV)
+X(D_XGE_MODE)
+X(E)
+X(ECP5_IS_GLOBAL)
+X(ER1)
+X(ER2)
+X(FEEDBK_PATH)
+X(FORCE_MAX_DELAY)
+X(FORCE_ZERO_BARREL_SHIFT)
+X(FREQ_LOCK_ACCURACY)
+X(GND)
+X(HYSTERESIS)
+X(ICP_CURRENT)
+X(IDDR71B)
+X(IDDRX1F)
+X(IDDRX2DQA)
+X(IDDRX2F)
+X(INIT)
+X(INIT0)
+X(INIT1)
+X(INITVAL)
+X(INJECT1_0)
+X(INJECT1_1)
+X(INTFB_WAKE)
+X(INT_LOCK_STICKY)
+X(INV)
+X(IOLTOMUX)
+X(IO_TYPE)
+X(KVCO)
+X(L6MUX21)
+X(LEGACY)
+X(LOC)
+X(LPF_CAPACITOR)
+X(LPF_RESISTOR)
+X(LSRIMUX)
+X(LSRMODE)
+X(LSROMUX)
+X(LUT0_INITVAL)
+X(LUT1_INITVAL)
+X(LUT4)
+X(M)
+X(MASK01)
+X(MASKPAT)
+X(MASKPAT_SOURCE)
+X(MCPAT)
+X(MCPAT_SOURCE)
+X(MFG1_TEST)
+X(MFG2_TEST)
+X(MFG_ENABLE_FILTEROPAMP)
+X(MFG_EN_UP)
+X(MFG_FLOAT_ICP)
+X(MFG_FORCE_VFILTER)
+X(MFG_GMCREF_SEL)
+X(MFG_GMC_GAIN)
+X(MFG_GMC_PRESET)
+X(MFG_GMC_RESET)
+X(MFG_GMC_TEST)
+X(MFG_ICP_TEST)
+X(MFG_LF_PRESET)
+X(MFG_LF_RESET)
+X(MFG_LF_RESGRND)
+X(MODE)
+X(MULT_BYPASS)
+X(OCEAMUX)
+X(OCEBMUX)
+X(OCER)
+X(ODDR71B)
+X(ODDRX1F)
+X(ODDRX2DQA)
+X(ODDRX2DQSB)
+X(ODDRX2F)
+X(OPENDRAIN)
+X(OSHX2A)
+X(OUTDIVIDER_MUXA)
+X(OUTDIVIDER_MUXB)
+X(OUTDIVIDER_MUXC)
+X(OUTDIVIDER_MUXD)
+X(PDPW16KD)
+X(PFUMX)
+X(PLLRST_ENA)
+X(PLL_LOCK_MODE)
+X(PULLMODE)
+X(Q)
+X(Q2)
+X(Q3)
+X(Q4)
+X(Q5)
+X(Q6)
+X(QWL)
+X(REFCK_DCBIAS_EN)
+X(REFCK_PWDNB)
+X(REFCK_RTERM)
+X(REFIN_RESET)
+X(REG0_LSRMODE)
+X(REG0_REGSET)
+X(REG0_SD)
+X(REG1_LSRMODE)
+X(REG1_REGSET)
+X(REG1_SD)
+X(REGMODE)
+X(REGMODE_A)
+X(REGMODE_B)
+X(REGSET)
+X(REG_FLAG_CLK)
+X(REG_INPUTA_CE)
+X(REG_INPUTA_CLK)
+X(REG_INPUTA_RST)
+X(REG_INPUTB_CE)
+X(REG_INPUTB_CLK)
+X(REG_INPUTB_RST)
+X(REG_INPUTC0_CLK)
+X(REG_INPUTC1_CLK)
+X(REG_INPUTC_CLK)
+X(REG_OPCODEIN_0_CE)
+X(REG_OPCODEIN_0_CLK)
+X(REG_OPCODEIN_0_RST)
+X(REG_OPCODEIN_1_CE)
+X(REG_OPCODEIN_1_CLK)
+X(REG_OPCODEIN_1_RST)
+X(REG_OPCODEOP0_0_CE)
+X(REG_OPCODEOP0_0_CLK)
+X(REG_OPCODEOP0_0_RST)
+X(REG_OPCODEOP0_1_CE)
+X(REG_OPCODEOP0_1_CLK)
+X(REG_OPCODEOP0_1_RST)
+X(REG_OPCODEOP1_0_CLK)
+X(REG_OPCODEOP1_1_CLK)
+X(REG_OUTPUT0_CLK)
+X(REG_OUTPUT1_CLK)
+X(REG_OUTPUT_CLK)
+X(REG_OUTPUT_RST)
+X(REG_PIPELINE_CE)
+X(REG_PIPELINE_CLK)
+X(REG_PIPELINE_RST)
+X(RESETMODE)
+X(RNDPAT)
+X(RSTAMUX)
+X(RSTBMUX)
+X(S0)
+X(S1)
+X(SD)
+X(SGSR)
+X(SLEWRATE)
+X(SOURCEB_MODE)
+X(STDBY_ENABLE)
+X(SYNCMODE)
+X(SYNC_ENABLE)
+X(T0)
+X(T1)
+X(TERMINATION)
+X(TILE_WIRE_ID)
+X(TRELLIS_DPR16X4)
+X(TRELLIS_FF)
+X(TRIMUX_TSREG)
+X(TSHX2DQA)
+X(TSHX2DQSA)
+X(USRMCLKI)
+X(USRMCLKO)
+X(USRMCLKTS)
+X(VCC)
+X(WCKMUX)
+X(WEAMUX)
+X(WEBMUX)
+X(WID)
+X(WREMUX)
+X(WRITEMODE_A)
+X(WRITEMODE_B)
+X(Y)
+X(ioff_dir)
+X(lfe5u_12f)
+X(lfe5u_25f)
+X(lfe5u_45f)
+X(lfe5u_85f)
+X(lfe5um5g_25f)
+X(lfe5um5g_45f)
+X(lfe5um5g_85f)
+X(lfe5um_25f)
+X(lfe5um_45f)
+X(lfe5um_85f)
+X(noglobal)
+X(pack)
+X(place)
+X(placer)
+X(route)
+X(router)
+X(syn_useioff)
diff --git a/ecp5/dcu_bitstream.h b/ecp5/dcu_bitstream.h
index 0c461a6b..4f0e63e1 100644
--- a/ecp5/dcu_bitstream.h
+++ b/ecp5/dcu_bitstream.h
@@ -1,504 +1,424 @@
tg.config.add_word("DCU.CH0_AUTO_CALIB_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_AUTO_CALIB_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_AUTO_CALIB_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_AUTO_FACQ_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_AUTO_FACQ_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_AUTO_FACQ_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_BAND_THRESHOLD",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_BAND_THRESHOLD"), Property(0)), 6));
+ parse_config_str(get_or_default(ci->params, id_CH0_BAND_THRESHOLD, Property(0)), 6));
tg.config.add_word("DCU.CH0_CALIB_CK_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_CALIB_CK_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_CALIB_CK_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH0_CC_MATCH_1",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_CC_MATCH_1"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH0_CC_MATCH_1, Property(0)), 10));
tg.config.add_word("DCU.CH0_CC_MATCH_2",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_CC_MATCH_2"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH0_CC_MATCH_2, Property(0)), 10));
tg.config.add_word("DCU.CH0_CC_MATCH_3",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_CC_MATCH_3"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH0_CC_MATCH_3, Property(0)), 10));
tg.config.add_word("DCU.CH0_CC_MATCH_4",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_CC_MATCH_4"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH0_CC_MATCH_4, Property(0)), 10));
tg.config.add_word("DCU.CH0_CDR_CNT4SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_CDR_CNT4SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_CDR_CNT4SEL, Property(0)), 2));
tg.config.add_word("DCU.CH0_CDR_CNT8SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_CDR_CNT8SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_CDR_CNT8SEL, Property(0)), 2));
tg.config.add_word("DCU.CH0_CTC_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_CTC_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_DCOATDCFG",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOATDCFG"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_DCOATDDLY",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOATDDLY"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_CTC_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH0_DCOATDCFG", parse_config_str(get_or_default(ci->params, id_CH0_DCOATDCFG, Property(0)), 2));
+tg.config.add_word("DCU.CH0_DCOATDDLY", parse_config_str(get_or_default(ci->params, id_CH0_DCOATDDLY, Property(0)), 2));
tg.config.add_word("DCU.CH0_DCOBYPSATD",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOBYPSATD"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_DCOCALDIV",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOCALDIV"), Property(0)), 3));
-tg.config.add_word("DCU.CH0_DCOCTLGI",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOCTLGI"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH0_DCOBYPSATD, Property(0)), 1));
+tg.config.add_word("DCU.CH0_DCOCALDIV", parse_config_str(get_or_default(ci->params, id_CH0_DCOCALDIV, Property(0)), 3));
+tg.config.add_word("DCU.CH0_DCOCTLGI", parse_config_str(get_or_default(ci->params, id_CH0_DCOCTLGI, Property(0)), 3));
tg.config.add_word("DCU.CH0_DCODISBDAVOID",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCODISBDAVOID"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_DCOFLTDAC",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOFLTDAC"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_DCOFTNRG",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOFTNRG"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH0_DCODISBDAVOID, Property(0)), 1));
+tg.config.add_word("DCU.CH0_DCOFLTDAC", parse_config_str(get_or_default(ci->params, id_CH0_DCOFLTDAC, Property(0)), 2));
+tg.config.add_word("DCU.CH0_DCOFTNRG", parse_config_str(get_or_default(ci->params, id_CH0_DCOFTNRG, Property(0)), 3));
tg.config.add_word("DCU.CH0_DCOIOSTUNE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOIOSTUNE"), Property(0)), 3));
-tg.config.add_word("DCU.CH0_DCOITUNE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOITUNE"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_DCOIOSTUNE, Property(0)), 3));
+tg.config.add_word("DCU.CH0_DCOITUNE", parse_config_str(get_or_default(ci->params, id_CH0_DCOITUNE, Property(0)), 2));
tg.config.add_word("DCU.CH0_DCOITUNE4LSB",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOITUNE4LSB"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH0_DCOITUNE4LSB, Property(0)), 3));
tg.config.add_word("DCU.CH0_DCOIUPDNX2",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOIUPDNX2"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_DCOIUPDNX2, Property(0)), 1));
tg.config.add_word("DCU.CH0_DCONUOFLSB",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCONUOFLSB"), Property(0)), 3));
-tg.config.add_word("DCU.CH0_DCOSCALEI",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOSCALEI"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_DCONUOFLSB, Property(0)), 3));
+tg.config.add_word("DCU.CH0_DCOSCALEI", parse_config_str(get_or_default(ci->params, id_CH0_DCOSCALEI, Property(0)), 2));
tg.config.add_word("DCU.CH0_DCOSTARTVAL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOSTARTVAL"), Property(0)), 3));
-tg.config.add_word("DCU.CH0_DCOSTEP",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DCOSTEP"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_DCOSTARTVAL, Property(0)), 3));
+tg.config.add_word("DCU.CH0_DCOSTEP", parse_config_str(get_or_default(ci->params, id_CH0_DCOSTEP, Property(0)), 2));
tg.config.add_word("DCU.CH0_DEC_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_DEC_BYPASS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_DEC_BYPASS, Property(0)), 1));
tg.config.add_word("DCU.CH0_ENABLE_CG_ALIGN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_ENABLE_CG_ALIGN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_ENABLE_CG_ALIGN, Property(0)), 1));
tg.config.add_word("DCU.CH0_ENC_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_ENC_BYPASS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_ENC_BYPASS, Property(0)), 1));
tg.config.add_word("DCU.CH0_FF_RX_F_CLK_DIS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_FF_RX_F_CLK_DIS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_FF_RX_F_CLK_DIS, Property(0)), 1));
tg.config.add_word("DCU.CH0_FF_RX_H_CLK_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_FF_RX_H_CLK_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_FF_RX_H_CLK_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_FF_TX_F_CLK_DIS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_FF_TX_F_CLK_DIS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_FF_TX_F_CLK_DIS, Property(0)), 1));
tg.config.add_word("DCU.CH0_FF_TX_H_CLK_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_FF_TX_H_CLK_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_FF_TX_H_CLK_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_GE_AN_ENABLE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_GE_AN_ENABLE"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_INVERT_RX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_INVERT_RX"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_INVERT_TX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_INVERT_TX"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_GE_AN_ENABLE, Property(0)), 1));
+tg.config.add_word("DCU.CH0_INVERT_RX", parse_config_str(get_or_default(ci->params, id_CH0_INVERT_RX, Property(0)), 1));
+tg.config.add_word("DCU.CH0_INVERT_TX", parse_config_str(get_or_default(ci->params, id_CH0_INVERT_TX, Property(0)), 1));
tg.config.add_word("DCU.CH0_LDR_CORE2TX_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_LDR_CORE2TX_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_LDR_CORE2TX_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH0_LDR_RX2CORE_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_LDR_RX2CORE_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_LDR_RX2CORE_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH0_LEQ_OFFSET_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_LEQ_OFFSET_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_LEQ_OFFSET_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH0_LEQ_OFFSET_TRIM",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_LEQ_OFFSET_TRIM"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH0_LEQ_OFFSET_TRIM, Property(0)), 3));
tg.config.add_word("DCU.CH0_LSM_DISABLE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_LSM_DISABLE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_LSM_DISABLE, Property(0)), 1));
tg.config.add_word("DCU.CH0_MATCH_2_ENABLE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_MATCH_2_ENABLE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_MATCH_2_ENABLE, Property(0)), 1));
tg.config.add_word("DCU.CH0_MATCH_4_ENABLE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_MATCH_4_ENABLE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_MATCH_4_ENABLE, Property(0)), 1));
tg.config.add_word("DCU.CH0_MIN_IPG_CNT",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_MIN_IPG_CNT"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_MIN_IPG_CNT, Property(0)), 2));
tg.config.add_word("DCU.CH0_PCIE_EI_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_PCIE_EI_EN"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_PCIE_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_PCIE_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_PCIE_EI_EN, Property(0)), 1));
+tg.config.add_word("DCU.CH0_PCIE_MODE", parse_config_str(get_or_default(ci->params, id_CH0_PCIE_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH0_PCS_DET_TIME_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_PCS_DET_TIME_SEL"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_PDEN_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_PDEN_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_PCS_DET_TIME_SEL, Property(0)), 2));
+tg.config.add_word("DCU.CH0_PDEN_SEL", parse_config_str(get_or_default(ci->params, id_CH0_PDEN_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH0_PRBS_ENABLE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_PRBS_ENABLE"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_PRBS_LOCK",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_PRBS_LOCK"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_PRBS_ENABLE, Property(0)), 1));
+tg.config.add_word("DCU.CH0_PRBS_LOCK", parse_config_str(get_or_default(ci->params, id_CH0_PRBS_LOCK, Property(0)), 1));
tg.config.add_word("DCU.CH0_PRBS_SELECTION",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_PRBS_SELECTION"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_PRBS_SELECTION, Property(0)), 1));
tg.config.add_word("DCU.CH0_RATE_MODE_RX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RATE_MODE_RX"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_RATE_MODE_RX, Property(0)), 1));
tg.config.add_word("DCU.CH0_RATE_MODE_TX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RATE_MODE_TX"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_RATE_MODE_TX, Property(0)), 1));
tg.config.add_word("DCU.CH0_RCV_DCC_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RCV_DCC_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_RCV_DCC_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_REG_BAND_OFFSET",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_REG_BAND_OFFSET"), Property(0)), 4));
+ parse_config_str(get_or_default(ci->params, id_CH0_REG_BAND_OFFSET, Property(0)), 4));
tg.config.add_word("DCU.CH0_REG_BAND_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_REG_BAND_SEL"), Property(0)), 6));
+ parse_config_str(get_or_default(ci->params, id_CH0_REG_BAND_SEL, Property(0)), 6));
tg.config.add_word("DCU.CH0_REG_IDAC_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_REG_IDAC_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_REG_IDAC_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_REG_IDAC_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_REG_IDAC_SEL"), Property(0)), 10));
-tg.config.add_word("DCU.CH0_REQ_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_REQ_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_REG_IDAC_SEL, Property(0)), 10));
+tg.config.add_word("DCU.CH0_REQ_EN", parse_config_str(get_or_default(ci->params, id_CH0_REQ_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_REQ_LVL_SET",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_REQ_LVL_SET"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_RIO_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RIO_MODE"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_RLOS_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RLOS_SEL"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_RPWDNB",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RPWDNB"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_RTERM_RX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RTERM_RX"), Property(0)), 5));
-tg.config.add_word("DCU.CH0_RTERM_TX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RTERM_TX"), Property(0)), 5));
-tg.config.add_word("DCU.CH0_RXIN_CM",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RXIN_CM"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_RXTERM_CM",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RXTERM_CM"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_REQ_LVL_SET, Property(0)), 2));
+tg.config.add_word("DCU.CH0_RIO_MODE", parse_config_str(get_or_default(ci->params, id_CH0_RIO_MODE, Property(0)), 1));
+tg.config.add_word("DCU.CH0_RLOS_SEL", parse_config_str(get_or_default(ci->params, id_CH0_RLOS_SEL, Property(0)), 1));
+tg.config.add_word("DCU.CH0_RPWDNB", parse_config_str(get_or_default(ci->params, id_CH0_RPWDNB, Property(0)), 1));
+tg.config.add_word("DCU.CH0_RTERM_RX", parse_config_str(get_or_default(ci->params, id_CH0_RTERM_RX, Property(0)), 5));
+tg.config.add_word("DCU.CH0_RTERM_TX", parse_config_str(get_or_default(ci->params, id_CH0_RTERM_TX, Property(0)), 5));
+tg.config.add_word("DCU.CH0_RXIN_CM", parse_config_str(get_or_default(ci->params, id_CH0_RXIN_CM, Property(0)), 2));
+tg.config.add_word("DCU.CH0_RXTERM_CM", parse_config_str(get_or_default(ci->params, id_CH0_RXTERM_CM, Property(0)), 2));
tg.config.add_word("DCU.CH0_RX_DCO_CK_DIV",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_DCO_CK_DIV"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH0_RX_DCO_CK_DIV, Property(0)), 3));
tg.config.add_word("DCU.CH0_RX_DIV11_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_DIV11_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_RX_DIV11_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH0_RX_GEAR_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_GEAR_BYPASS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_RX_GEAR_BYPASS, Property(0)), 1));
tg.config.add_word("DCU.CH0_RX_GEAR_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_GEAR_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_RX_GEAR_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH0_RX_LOS_CEQ",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_LOS_CEQ"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_RX_LOS_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_LOS_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_RX_LOS_CEQ, Property(0)), 2));
+tg.config.add_word("DCU.CH0_RX_LOS_EN", parse_config_str(get_or_default(ci->params, id_CH0_RX_LOS_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_RX_LOS_HYST_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_LOS_HYST_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_RX_LOS_HYST_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_RX_LOS_LVL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_LOS_LVL"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH0_RX_LOS_LVL, Property(0)), 3));
tg.config.add_word("DCU.CH0_RX_RATE_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_RATE_SEL"), Property(0)), 4));
+ parse_config_str(get_or_default(ci->params, id_CH0_RX_RATE_SEL, Property(0)), 4));
tg.config.add_word("DCU.CH0_RX_SB_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_RX_SB_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_SB_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_SB_BYPASS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_RX_SB_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH0_SB_BYPASS", parse_config_str(get_or_default(ci->params, id_CH0_SB_BYPASS, Property(0)), 1));
tg.config.add_word("DCU.CH0_SEL_SD_RX_CLK",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_SEL_SD_RX_CLK"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_SEL_SD_RX_CLK, Property(0)), 1));
tg.config.add_word("DCU.CH0_TDRV_DAT_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_DAT_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_DAT_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH0_TDRV_POST_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_POST_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_POST_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_TDRV_PRE_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_PRE_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_PRE_EN, Property(0)), 1));
tg.config.add_word("DCU.CH0_TDRV_SLICE0_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE0_CUR"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE0_CUR, Property(0)), 3));
tg.config.add_word("DCU.CH0_TDRV_SLICE0_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE0_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE0_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH0_TDRV_SLICE1_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE1_CUR"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE1_CUR, Property(0)), 3));
tg.config.add_word("DCU.CH0_TDRV_SLICE1_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE1_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE1_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH0_TDRV_SLICE2_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE2_CUR"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE2_CUR, Property(0)), 2));
tg.config.add_word("DCU.CH0_TDRV_SLICE2_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE2_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE2_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH0_TDRV_SLICE3_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE3_CUR"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE3_CUR, Property(0)), 2));
tg.config.add_word("DCU.CH0_TDRV_SLICE3_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE3_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE3_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH0_TDRV_SLICE4_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE4_CUR"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE4_CUR, Property(0)), 2));
tg.config.add_word("DCU.CH0_TDRV_SLICE4_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE4_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE4_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH0_TDRV_SLICE5_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE5_CUR"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE5_CUR, Property(0)), 2));
tg.config.add_word("DCU.CH0_TDRV_SLICE5_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TDRV_SLICE5_SEL"), Property(0)), 2));
-tg.config.add_word("DCU.CH0_TPWDNB",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TPWDNB"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_TX_CM_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_CM_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH0_TDRV_SLICE5_SEL, Property(0)), 2));
+tg.config.add_word("DCU.CH0_TPWDNB", parse_config_str(get_or_default(ci->params, id_CH0_TPWDNB, Property(0)), 1));
+tg.config.add_word("DCU.CH0_TX_CM_SEL", parse_config_str(get_or_default(ci->params, id_CH0_TX_CM_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH0_TX_DIV11_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_DIV11_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_TX_DIV11_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH0_TX_GEAR_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_GEAR_BYPASS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_TX_GEAR_BYPASS, Property(0)), 1));
tg.config.add_word("DCU.CH0_TX_GEAR_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_GEAR_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_TX_GEAR_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH0_TX_POST_SIGN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_POST_SIGN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_TX_POST_SIGN, Property(0)), 1));
tg.config.add_word("DCU.CH0_TX_PRE_SIGN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_TX_PRE_SIGN"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_UC_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_UC_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_TX_PRE_SIGN, Property(0)), 1));
+tg.config.add_word("DCU.CH0_UC_MODE", parse_config_str(get_or_default(ci->params, id_CH0_UC_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH0_UDF_COMMA_A",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_UDF_COMMA_A"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH0_UDF_COMMA_A, Property(0)), 10));
tg.config.add_word("DCU.CH0_UDF_COMMA_B",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_UDF_COMMA_B"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH0_UDF_COMMA_B, Property(0)), 10));
tg.config.add_word("DCU.CH0_UDF_COMMA_MASK",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_UDF_COMMA_MASK"), Property(0)), 10));
-tg.config.add_word("DCU.CH0_WA_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_WA_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH0_WA_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH0_WA_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH0_UDF_COMMA_MASK, Property(0)), 10));
+tg.config.add_word("DCU.CH0_WA_BYPASS", parse_config_str(get_or_default(ci->params, id_CH0_WA_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH0_WA_MODE", parse_config_str(get_or_default(ci->params, id_CH0_WA_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH1_AUTO_CALIB_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_AUTO_CALIB_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_AUTO_CALIB_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_AUTO_FACQ_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_AUTO_FACQ_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_AUTO_FACQ_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_BAND_THRESHOLD",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_BAND_THRESHOLD"), Property(0)), 6));
+ parse_config_str(get_or_default(ci->params, id_CH1_BAND_THRESHOLD, Property(0)), 6));
tg.config.add_word("DCU.CH1_CALIB_CK_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_CALIB_CK_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_CALIB_CK_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH1_CC_MATCH_1",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_CC_MATCH_1"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH1_CC_MATCH_1, Property(0)), 10));
tg.config.add_word("DCU.CH1_CC_MATCH_2",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_CC_MATCH_2"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH1_CC_MATCH_2, Property(0)), 10));
tg.config.add_word("DCU.CH1_CC_MATCH_3",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_CC_MATCH_3"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH1_CC_MATCH_3, Property(0)), 10));
tg.config.add_word("DCU.CH1_CC_MATCH_4",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_CC_MATCH_4"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH1_CC_MATCH_4, Property(0)), 10));
tg.config.add_word("DCU.CH1_CDR_CNT4SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_CDR_CNT4SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_CDR_CNT4SEL, Property(0)), 2));
tg.config.add_word("DCU.CH1_CDR_CNT8SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_CDR_CNT8SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_CDR_CNT8SEL, Property(0)), 2));
tg.config.add_word("DCU.CH1_CTC_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_CTC_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_DCOATDCFG",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOATDCFG"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_DCOATDDLY",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOATDDLY"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_CTC_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH1_DCOATDCFG", parse_config_str(get_or_default(ci->params, id_CH1_DCOATDCFG, Property(0)), 2));
+tg.config.add_word("DCU.CH1_DCOATDDLY", parse_config_str(get_or_default(ci->params, id_CH1_DCOATDDLY, Property(0)), 2));
tg.config.add_word("DCU.CH1_DCOBYPSATD",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOBYPSATD"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_DCOCALDIV",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOCALDIV"), Property(0)), 3));
-tg.config.add_word("DCU.CH1_DCOCTLGI",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOCTLGI"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH1_DCOBYPSATD, Property(0)), 1));
+tg.config.add_word("DCU.CH1_DCOCALDIV", parse_config_str(get_or_default(ci->params, id_CH1_DCOCALDIV, Property(0)), 3));
+tg.config.add_word("DCU.CH1_DCOCTLGI", parse_config_str(get_or_default(ci->params, id_CH1_DCOCTLGI, Property(0)), 3));
tg.config.add_word("DCU.CH1_DCODISBDAVOID",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCODISBDAVOID"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_DCOFLTDAC",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOFLTDAC"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_DCOFTNRG",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOFTNRG"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH1_DCODISBDAVOID, Property(0)), 1));
+tg.config.add_word("DCU.CH1_DCOFLTDAC", parse_config_str(get_or_default(ci->params, id_CH1_DCOFLTDAC, Property(0)), 2));
+tg.config.add_word("DCU.CH1_DCOFTNRG", parse_config_str(get_or_default(ci->params, id_CH1_DCOFTNRG, Property(0)), 3));
tg.config.add_word("DCU.CH1_DCOIOSTUNE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOIOSTUNE"), Property(0)), 3));
-tg.config.add_word("DCU.CH1_DCOITUNE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOITUNE"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_DCOIOSTUNE, Property(0)), 3));
+tg.config.add_word("DCU.CH1_DCOITUNE", parse_config_str(get_or_default(ci->params, id_CH1_DCOITUNE, Property(0)), 2));
tg.config.add_word("DCU.CH1_DCOITUNE4LSB",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOITUNE4LSB"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH1_DCOITUNE4LSB, Property(0)), 3));
tg.config.add_word("DCU.CH1_DCOIUPDNX2",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOIUPDNX2"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_DCOIUPDNX2, Property(0)), 1));
tg.config.add_word("DCU.CH1_DCONUOFLSB",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCONUOFLSB"), Property(0)), 3));
-tg.config.add_word("DCU.CH1_DCOSCALEI",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOSCALEI"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_DCONUOFLSB, Property(0)), 3));
+tg.config.add_word("DCU.CH1_DCOSCALEI", parse_config_str(get_or_default(ci->params, id_CH1_DCOSCALEI, Property(0)), 2));
tg.config.add_word("DCU.CH1_DCOSTARTVAL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOSTARTVAL"), Property(0)), 3));
-tg.config.add_word("DCU.CH1_DCOSTEP",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DCOSTEP"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_DCOSTARTVAL, Property(0)), 3));
+tg.config.add_word("DCU.CH1_DCOSTEP", parse_config_str(get_or_default(ci->params, id_CH1_DCOSTEP, Property(0)), 2));
tg.config.add_word("DCU.CH1_DEC_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_DEC_BYPASS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_DEC_BYPASS, Property(0)), 1));
tg.config.add_word("DCU.CH1_ENABLE_CG_ALIGN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_ENABLE_CG_ALIGN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_ENABLE_CG_ALIGN, Property(0)), 1));
tg.config.add_word("DCU.CH1_ENC_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_ENC_BYPASS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_ENC_BYPASS, Property(0)), 1));
tg.config.add_word("DCU.CH1_FF_RX_F_CLK_DIS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_FF_RX_F_CLK_DIS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_FF_RX_F_CLK_DIS, Property(0)), 1));
tg.config.add_word("DCU.CH1_FF_RX_H_CLK_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_FF_RX_H_CLK_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_FF_RX_H_CLK_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_FF_TX_F_CLK_DIS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_FF_TX_F_CLK_DIS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_FF_TX_F_CLK_DIS, Property(0)), 1));
tg.config.add_word("DCU.CH1_FF_TX_H_CLK_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_FF_TX_H_CLK_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_FF_TX_H_CLK_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_GE_AN_ENABLE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_GE_AN_ENABLE"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_INVERT_RX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_INVERT_RX"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_INVERT_TX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_INVERT_TX"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_GE_AN_ENABLE, Property(0)), 1));
+tg.config.add_word("DCU.CH1_INVERT_RX", parse_config_str(get_or_default(ci->params, id_CH1_INVERT_RX, Property(0)), 1));
+tg.config.add_word("DCU.CH1_INVERT_TX", parse_config_str(get_or_default(ci->params, id_CH1_INVERT_TX, Property(0)), 1));
tg.config.add_word("DCU.CH1_LDR_CORE2TX_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_LDR_CORE2TX_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_LDR_CORE2TX_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH1_LDR_RX2CORE_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_LDR_RX2CORE_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_LDR_RX2CORE_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH1_LEQ_OFFSET_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_LEQ_OFFSET_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_LEQ_OFFSET_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH1_LEQ_OFFSET_TRIM",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_LEQ_OFFSET_TRIM"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH1_LEQ_OFFSET_TRIM, Property(0)), 3));
tg.config.add_word("DCU.CH1_LSM_DISABLE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_LSM_DISABLE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_LSM_DISABLE, Property(0)), 1));
tg.config.add_word("DCU.CH1_MATCH_2_ENABLE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_MATCH_2_ENABLE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_MATCH_2_ENABLE, Property(0)), 1));
tg.config.add_word("DCU.CH1_MATCH_4_ENABLE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_MATCH_4_ENABLE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_MATCH_4_ENABLE, Property(0)), 1));
tg.config.add_word("DCU.CH1_MIN_IPG_CNT",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_MIN_IPG_CNT"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_MIN_IPG_CNT, Property(0)), 2));
tg.config.add_word("DCU.CH1_PCIE_EI_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_PCIE_EI_EN"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_PCIE_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_PCIE_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_PCIE_EI_EN, Property(0)), 1));
+tg.config.add_word("DCU.CH1_PCIE_MODE", parse_config_str(get_or_default(ci->params, id_CH1_PCIE_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH1_PCS_DET_TIME_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_PCS_DET_TIME_SEL"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_PDEN_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_PDEN_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_PCS_DET_TIME_SEL, Property(0)), 2));
+tg.config.add_word("DCU.CH1_PDEN_SEL", parse_config_str(get_or_default(ci->params, id_CH1_PDEN_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH1_PRBS_ENABLE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_PRBS_ENABLE"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_PRBS_LOCK",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_PRBS_LOCK"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_PRBS_ENABLE, Property(0)), 1));
+tg.config.add_word("DCU.CH1_PRBS_LOCK", parse_config_str(get_or_default(ci->params, id_CH1_PRBS_LOCK, Property(0)), 1));
tg.config.add_word("DCU.CH1_PRBS_SELECTION",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_PRBS_SELECTION"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_PRBS_SELECTION, Property(0)), 1));
tg.config.add_word("DCU.CH1_RATE_MODE_RX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RATE_MODE_RX"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_RATE_MODE_RX, Property(0)), 1));
tg.config.add_word("DCU.CH1_RATE_MODE_TX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RATE_MODE_TX"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_RATE_MODE_TX, Property(0)), 1));
tg.config.add_word("DCU.CH1_RCV_DCC_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RCV_DCC_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_RCV_DCC_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_REG_BAND_OFFSET",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_REG_BAND_OFFSET"), Property(0)), 4));
+ parse_config_str(get_or_default(ci->params, id_CH1_REG_BAND_OFFSET, Property(0)), 4));
tg.config.add_word("DCU.CH1_REG_BAND_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_REG_BAND_SEL"), Property(0)), 6));
+ parse_config_str(get_or_default(ci->params, id_CH1_REG_BAND_SEL, Property(0)), 6));
tg.config.add_word("DCU.CH1_REG_IDAC_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_REG_IDAC_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_REG_IDAC_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_REG_IDAC_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_REG_IDAC_SEL"), Property(0)), 10));
-tg.config.add_word("DCU.CH1_REQ_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_REQ_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_REG_IDAC_SEL, Property(0)), 10));
+tg.config.add_word("DCU.CH1_REQ_EN", parse_config_str(get_or_default(ci->params, id_CH1_REQ_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_REQ_LVL_SET",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_REQ_LVL_SET"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_RIO_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RIO_MODE"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_RLOS_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RLOS_SEL"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_RPWDNB",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RPWDNB"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_RTERM_RX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RTERM_RX"), Property(0)), 5));
-tg.config.add_word("DCU.CH1_RTERM_TX",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RTERM_TX"), Property(0)), 5));
-tg.config.add_word("DCU.CH1_RXIN_CM",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RXIN_CM"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_RXTERM_CM",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RXTERM_CM"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_REQ_LVL_SET, Property(0)), 2));
+tg.config.add_word("DCU.CH1_RIO_MODE", parse_config_str(get_or_default(ci->params, id_CH1_RIO_MODE, Property(0)), 1));
+tg.config.add_word("DCU.CH1_RLOS_SEL", parse_config_str(get_or_default(ci->params, id_CH1_RLOS_SEL, Property(0)), 1));
+tg.config.add_word("DCU.CH1_RPWDNB", parse_config_str(get_or_default(ci->params, id_CH1_RPWDNB, Property(0)), 1));
+tg.config.add_word("DCU.CH1_RTERM_RX", parse_config_str(get_or_default(ci->params, id_CH1_RTERM_RX, Property(0)), 5));
+tg.config.add_word("DCU.CH1_RTERM_TX", parse_config_str(get_or_default(ci->params, id_CH1_RTERM_TX, Property(0)), 5));
+tg.config.add_word("DCU.CH1_RXIN_CM", parse_config_str(get_or_default(ci->params, id_CH1_RXIN_CM, Property(0)), 2));
+tg.config.add_word("DCU.CH1_RXTERM_CM", parse_config_str(get_or_default(ci->params, id_CH1_RXTERM_CM, Property(0)), 2));
tg.config.add_word("DCU.CH1_RX_DCO_CK_DIV",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_DCO_CK_DIV"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH1_RX_DCO_CK_DIV, Property(0)), 3));
tg.config.add_word("DCU.CH1_RX_DIV11_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_DIV11_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_RX_DIV11_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH1_RX_GEAR_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_GEAR_BYPASS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_RX_GEAR_BYPASS, Property(0)), 1));
tg.config.add_word("DCU.CH1_RX_GEAR_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_GEAR_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_RX_GEAR_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH1_RX_LOS_CEQ",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_LOS_CEQ"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_RX_LOS_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_LOS_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_RX_LOS_CEQ, Property(0)), 2));
+tg.config.add_word("DCU.CH1_RX_LOS_EN", parse_config_str(get_or_default(ci->params, id_CH1_RX_LOS_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_RX_LOS_HYST_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_LOS_HYST_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_RX_LOS_HYST_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_RX_LOS_LVL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_LOS_LVL"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH1_RX_LOS_LVL, Property(0)), 3));
tg.config.add_word("DCU.CH1_RX_RATE_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_RATE_SEL"), Property(0)), 4));
+ parse_config_str(get_or_default(ci->params, id_CH1_RX_RATE_SEL, Property(0)), 4));
tg.config.add_word("DCU.CH1_RX_SB_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_RX_SB_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_SB_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_SB_BYPASS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_RX_SB_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH1_SB_BYPASS", parse_config_str(get_or_default(ci->params, id_CH1_SB_BYPASS, Property(0)), 1));
tg.config.add_word("DCU.CH1_SEL_SD_RX_CLK",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_SEL_SD_RX_CLK"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_SEL_SD_RX_CLK, Property(0)), 1));
tg.config.add_word("DCU.CH1_TDRV_DAT_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_DAT_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_DAT_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH1_TDRV_POST_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_POST_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_POST_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_TDRV_PRE_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_PRE_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_PRE_EN, Property(0)), 1));
tg.config.add_word("DCU.CH1_TDRV_SLICE0_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE0_CUR"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE0_CUR, Property(0)), 3));
tg.config.add_word("DCU.CH1_TDRV_SLICE0_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE0_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE0_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH1_TDRV_SLICE1_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE1_CUR"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE1_CUR, Property(0)), 3));
tg.config.add_word("DCU.CH1_TDRV_SLICE1_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE1_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE1_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH1_TDRV_SLICE2_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE2_CUR"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE2_CUR, Property(0)), 2));
tg.config.add_word("DCU.CH1_TDRV_SLICE2_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE2_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE2_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH1_TDRV_SLICE3_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE3_CUR"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE3_CUR, Property(0)), 2));
tg.config.add_word("DCU.CH1_TDRV_SLICE3_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE3_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE3_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH1_TDRV_SLICE4_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE4_CUR"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE4_CUR, Property(0)), 2));
tg.config.add_word("DCU.CH1_TDRV_SLICE4_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE4_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE4_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH1_TDRV_SLICE5_CUR",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE5_CUR"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE5_CUR, Property(0)), 2));
tg.config.add_word("DCU.CH1_TDRV_SLICE5_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TDRV_SLICE5_SEL"), Property(0)), 2));
-tg.config.add_word("DCU.CH1_TPWDNB",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TPWDNB"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_TX_CM_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_CM_SEL"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_CH1_TDRV_SLICE5_SEL, Property(0)), 2));
+tg.config.add_word("DCU.CH1_TPWDNB", parse_config_str(get_or_default(ci->params, id_CH1_TPWDNB, Property(0)), 1));
+tg.config.add_word("DCU.CH1_TX_CM_SEL", parse_config_str(get_or_default(ci->params, id_CH1_TX_CM_SEL, Property(0)), 2));
tg.config.add_word("DCU.CH1_TX_DIV11_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_DIV11_SEL"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_TX_DIV11_SEL, Property(0)), 1));
tg.config.add_word("DCU.CH1_TX_GEAR_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_GEAR_BYPASS"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_TX_GEAR_BYPASS, Property(0)), 1));
tg.config.add_word("DCU.CH1_TX_GEAR_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_GEAR_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_TX_GEAR_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH1_TX_POST_SIGN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_POST_SIGN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_TX_POST_SIGN, Property(0)), 1));
tg.config.add_word("DCU.CH1_TX_PRE_SIGN",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_TX_PRE_SIGN"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_UC_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_UC_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_TX_PRE_SIGN, Property(0)), 1));
+tg.config.add_word("DCU.CH1_UC_MODE", parse_config_str(get_or_default(ci->params, id_CH1_UC_MODE, Property(0)), 1));
tg.config.add_word("DCU.CH1_UDF_COMMA_A",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_UDF_COMMA_A"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH1_UDF_COMMA_A, Property(0)), 10));
tg.config.add_word("DCU.CH1_UDF_COMMA_B",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_UDF_COMMA_B"), Property(0)), 10));
+ parse_config_str(get_or_default(ci->params, id_CH1_UDF_COMMA_B, Property(0)), 10));
tg.config.add_word("DCU.CH1_UDF_COMMA_MASK",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_UDF_COMMA_MASK"), Property(0)), 10));
-tg.config.add_word("DCU.CH1_WA_BYPASS",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_WA_BYPASS"), Property(0)), 1));
-tg.config.add_word("DCU.CH1_WA_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("CH1_WA_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_CH1_UDF_COMMA_MASK, Property(0)), 10));
+tg.config.add_word("DCU.CH1_WA_BYPASS", parse_config_str(get_or_default(ci->params, id_CH1_WA_BYPASS, Property(0)), 1));
+tg.config.add_word("DCU.CH1_WA_MODE", parse_config_str(get_or_default(ci->params, id_CH1_WA_MODE, Property(0)), 1));
tg.config.add_word("DCU.D_BITCLK_FROM_ND_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("D_BITCLK_FROM_ND_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_D_BITCLK_FROM_ND_EN, Property(0)), 1));
tg.config.add_word("DCU.D_BITCLK_LOCAL_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("D_BITCLK_LOCAL_EN"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_D_BITCLK_LOCAL_EN, Property(0)), 1));
tg.config.add_word("DCU.D_BITCLK_ND_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("D_BITCLK_ND_EN"), Property(0)), 1));
-tg.config.add_word("DCU.D_BUS8BIT_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("D_BUS8BIT_SEL"), Property(0)), 1));
-tg.config.add_word("DCU.D_CDR_LOL_SET",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CDR_LOL_SET"), Property(0)), 2));
-tg.config.add_word("DCU.D_CMUSETBIASI",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETBIASI"), Property(0)), 2));
-tg.config.add_word("DCU.D_CMUSETI4CPP",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETI4CPP"), Property(0)), 4));
-tg.config.add_word("DCU.D_CMUSETI4CPZ",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETI4CPZ"), Property(0)), 4));
-tg.config.add_word("DCU.D_CMUSETI4VCO",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETI4VCO"), Property(0)), 2));
-tg.config.add_word("DCU.D_CMUSETICP4P",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETICP4P"), Property(0)), 2));
-tg.config.add_word("DCU.D_CMUSETICP4Z",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETICP4Z"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_D_BITCLK_ND_EN, Property(0)), 1));
+tg.config.add_word("DCU.D_BUS8BIT_SEL", parse_config_str(get_or_default(ci->params, id_D_BUS8BIT_SEL, Property(0)), 1));
+tg.config.add_word("DCU.D_CDR_LOL_SET", parse_config_str(get_or_default(ci->params, id_D_CDR_LOL_SET, Property(0)), 2));
+tg.config.add_word("DCU.D_CMUSETBIASI", parse_config_str(get_or_default(ci->params, id_D_CMUSETBIASI, Property(0)), 2));
+tg.config.add_word("DCU.D_CMUSETI4CPP", parse_config_str(get_or_default(ci->params, id_D_CMUSETI4CPP, Property(0)), 4));
+tg.config.add_word("DCU.D_CMUSETI4CPZ", parse_config_str(get_or_default(ci->params, id_D_CMUSETI4CPZ, Property(0)), 4));
+tg.config.add_word("DCU.D_CMUSETI4VCO", parse_config_str(get_or_default(ci->params, id_D_CMUSETI4VCO, Property(0)), 2));
+tg.config.add_word("DCU.D_CMUSETICP4P", parse_config_str(get_or_default(ci->params, id_D_CMUSETICP4P, Property(0)), 2));
+tg.config.add_word("DCU.D_CMUSETICP4Z", parse_config_str(get_or_default(ci->params, id_D_CMUSETICP4Z, Property(0)), 3));
tg.config.add_word("DCU.D_CMUSETINITVCT",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETINITVCT"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_D_CMUSETINITVCT, Property(0)), 2));
tg.config.add_word("DCU.D_CMUSETISCL4VCO",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETISCL4VCO"), Property(0)), 3));
-tg.config.add_word("DCU.D_CMUSETP1GM",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETP1GM"), Property(0)), 3));
-tg.config.add_word("DCU.D_CMUSETP2AGM",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETP2AGM"), Property(0)), 3));
-tg.config.add_word("DCU.D_CMUSETZGM",
- parse_config_str(get_or_default(ci->params, ctx->id("D_CMUSETZGM"), Property(0)), 3));
+ parse_config_str(get_or_default(ci->params, id_D_CMUSETISCL4VCO, Property(0)), 3));
+tg.config.add_word("DCU.D_CMUSETP1GM", parse_config_str(get_or_default(ci->params, id_D_CMUSETP1GM, Property(0)), 3));
+tg.config.add_word("DCU.D_CMUSETP2AGM", parse_config_str(get_or_default(ci->params, id_D_CMUSETP2AGM, Property(0)), 3));
+tg.config.add_word("DCU.D_CMUSETZGM", parse_config_str(get_or_default(ci->params, id_D_CMUSETZGM, Property(0)), 3));
tg.config.add_word("DCU.D_DCO_CALIB_TIME_SEL",
- parse_config_str(get_or_default(ci->params, ctx->id("D_DCO_CALIB_TIME_SEL"), Property(0)), 2));
-tg.config.add_word("DCU.D_HIGH_MARK",
- parse_config_str(get_or_default(ci->params, ctx->id("D_HIGH_MARK"), Property(0)), 4));
-tg.config.add_word("DCU.D_IB_PWDNB",
- parse_config_str(get_or_default(ci->params, ctx->id("D_IB_PWDNB"), Property(0)), 1));
-tg.config.add_word("DCU.D_ISETLOS", parse_config_str(get_or_default(ci->params, ctx->id("D_ISETLOS"), Property(0)), 8));
-tg.config.add_word("DCU.D_LOW_MARK",
- parse_config_str(get_or_default(ci->params, ctx->id("D_LOW_MARK"), Property(0)), 4));
-tg.config.add_word("DCU.D_MACROPDB",
- parse_config_str(get_or_default(ci->params, ctx->id("D_MACROPDB"), Property(0)), 1));
-tg.config.add_word("DCU.D_PD_ISET", parse_config_str(get_or_default(ci->params, ctx->id("D_PD_ISET"), Property(0)), 2));
-tg.config.add_word("DCU.D_PLL_LOL_SET",
- parse_config_str(get_or_default(ci->params, ctx->id("D_PLL_LOL_SET"), Property(0)), 2));
-tg.config.add_word("DCU.D_REFCK_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("D_REFCK_MODE"), Property(0)), 3));
-tg.config.add_word("DCU.D_REQ_ISET",
- parse_config_str(get_or_default(ci->params, ctx->id("D_REQ_ISET"), Property(0)), 3));
-tg.config.add_word("DCU.D_RG_EN", parse_config_str(get_or_default(ci->params, ctx->id("D_RG_EN"), Property(0)), 1));
-tg.config.add_word("DCU.D_RG_SET", parse_config_str(get_or_default(ci->params, ctx->id("D_RG_SET"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_D_DCO_CALIB_TIME_SEL, Property(0)), 2));
+tg.config.add_word("DCU.D_HIGH_MARK", parse_config_str(get_or_default(ci->params, id_D_HIGH_MARK, Property(0)), 4));
+tg.config.add_word("DCU.D_IB_PWDNB", parse_config_str(get_or_default(ci->params, id_D_IB_PWDNB, Property(0)), 1));
+tg.config.add_word("DCU.D_ISETLOS", parse_config_str(get_or_default(ci->params, id_D_ISETLOS, Property(0)), 8));
+tg.config.add_word("DCU.D_LOW_MARK", parse_config_str(get_or_default(ci->params, id_D_LOW_MARK, Property(0)), 4));
+tg.config.add_word("DCU.D_MACROPDB", parse_config_str(get_or_default(ci->params, id_D_MACROPDB, Property(0)), 1));
+tg.config.add_word("DCU.D_PD_ISET", parse_config_str(get_or_default(ci->params, id_D_PD_ISET, Property(0)), 2));
+tg.config.add_word("DCU.D_PLL_LOL_SET", parse_config_str(get_or_default(ci->params, id_D_PLL_LOL_SET, Property(0)), 2));
+tg.config.add_word("DCU.D_REFCK_MODE", parse_config_str(get_or_default(ci->params, id_D_REFCK_MODE, Property(0)), 3));
+tg.config.add_word("DCU.D_REQ_ISET", parse_config_str(get_or_default(ci->params, id_D_REQ_ISET, Property(0)), 3));
+tg.config.add_word("DCU.D_RG_EN", parse_config_str(get_or_default(ci->params, id_D_RG_EN, Property(0)), 1));
+tg.config.add_word("DCU.D_RG_SET", parse_config_str(get_or_default(ci->params, id_D_RG_SET, Property(0)), 2));
tg.config.add_word("DCU.D_SETICONST_AUX",
- parse_config_str(get_or_default(ci->params, ctx->id("D_SETICONST_AUX"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_D_SETICONST_AUX, Property(0)), 2));
tg.config.add_word("DCU.D_SETICONST_CH",
- parse_config_str(get_or_default(ci->params, ctx->id("D_SETICONST_CH"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_D_SETICONST_CH, Property(0)), 2));
tg.config.add_word("DCU.D_SETIRPOLY_AUX",
- parse_config_str(get_or_default(ci->params, ctx->id("D_SETIRPOLY_AUX"), Property(0)), 2));
+ parse_config_str(get_or_default(ci->params, id_D_SETIRPOLY_AUX, Property(0)), 2));
tg.config.add_word("DCU.D_SETIRPOLY_CH",
- parse_config_str(get_or_default(ci->params, ctx->id("D_SETIRPOLY_CH"), Property(0)), 2));
-tg.config.add_word("DCU.D_SETPLLRC",
- parse_config_str(get_or_default(ci->params, ctx->id("D_SETPLLRC"), Property(0)), 6));
+ parse_config_str(get_or_default(ci->params, id_D_SETIRPOLY_CH, Property(0)), 2));
+tg.config.add_word("DCU.D_SETPLLRC", parse_config_str(get_or_default(ci->params, id_D_SETPLLRC, Property(0)), 6));
tg.config.add_word("DCU.D_SYNC_LOCAL_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("D_SYNC_LOCAL_EN"), Property(0)), 1));
-tg.config.add_word("DCU.D_SYNC_ND_EN",
- parse_config_str(get_or_default(ci->params, ctx->id("D_SYNC_ND_EN"), Property(0)), 1));
-tg.config.add_word("DCU.D_TXPLL_PWDNB",
- parse_config_str(get_or_default(ci->params, ctx->id("D_TXPLL_PWDNB"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_D_SYNC_LOCAL_EN, Property(0)), 1));
+tg.config.add_word("DCU.D_SYNC_ND_EN", parse_config_str(get_or_default(ci->params, id_D_SYNC_ND_EN, Property(0)), 1));
+tg.config.add_word("DCU.D_TXPLL_PWDNB", parse_config_str(get_or_default(ci->params, id_D_TXPLL_PWDNB, Property(0)), 1));
tg.config.add_word("DCU.D_TX_VCO_CK_DIV",
- parse_config_str(get_or_default(ci->params, ctx->id("D_TX_VCO_CK_DIV"), Property(0)), 3));
-tg.config.add_word("DCU.D_XGE_MODE",
- parse_config_str(get_or_default(ci->params, ctx->id("D_XGE_MODE"), Property(0)), 1));
+ parse_config_str(get_or_default(ci->params, id_D_TX_VCO_CK_DIV, Property(0)), 3));
+tg.config.add_word("DCU.D_XGE_MODE", parse_config_str(get_or_default(ci->params, id_D_XGE_MODE, Property(0)), 1));
diff --git a/ecp5/globals.cc b/ecp5/globals.cc
index cc2208e0..844c596b 100644
--- a/ecp5/globals.cc
+++ b/ecp5/globals.cc
@@ -299,8 +299,8 @@ class Ecp5GlobalRouter
dedicated_routing = false;
if (drv.cell == nullptr) {
return 0;
- } else if (drv.cell->attrs.count(ctx->id("BEL"))) {
- drv_bel = ctx->getBelByNameStr(drv.cell->attrs.at(ctx->id("BEL")).as_string());
+ } else if (drv.cell->attrs.count(id_BEL)) {
+ drv_bel = ctx->getBelByNameStr(drv.cell->attrs.at(id_BEL).as_string());
} else {
// Check if driver is a singleton
BelId last_bel;
@@ -399,7 +399,7 @@ class Ecp5GlobalRouter
{
BelId best_bel;
WireId best_bel_pclkcib;
- bool using_ce = get_net_or_empty(dcc, ctx->id("CE")) != nullptr;
+ bool using_ce = get_net_or_empty(dcc, id_CE) != nullptr;
wirelen_t best_wirelen = 9999999;
bool dedicated_routing = false;
for (auto bel : ctx->getBels()) {
@@ -492,8 +492,8 @@ class Ecp5GlobalRouter
dccptr = dcc.get();
ctx->cells[dcc->name] = std::move(dcc);
}
- glbptr->attrs[ctx->id("ECP5_IS_GLOBAL")] = 1;
- if (str_or_default(dccptr->attrs, ctx->id("BEL"), "") == "")
+ glbptr->attrs[id_ECP5_IS_GLOBAL] = 1;
+ if (str_or_default(dccptr->attrs, id_BEL, "") == "")
place_dcc_dcs(dccptr);
return glbptr;
}
@@ -514,8 +514,8 @@ class Ecp5GlobalRouter
log_info("Promoting globals...\n");
auto clocks = get_clocks();
for (auto clock : clocks) {
- bool is_noglobal = bool_or_default(clock->attrs, ctx->id("noglobal"), false) ||
- bool_or_default(clock->attrs, ctx->id("ECP5_IS_GLOBAL"), false);
+ bool is_noglobal = bool_or_default(clock->attrs, id_noglobal, false) ||
+ bool_or_default(clock->attrs, id_ECP5_IS_GLOBAL, false);
if (is_noglobal)
continue;
log_info(" promoting clock net %s to global network\n", clock->name.c_str(ctx));
diff --git a/ecp5/lpf.cc b/ecp5/lpf.cc
index 3fd840cd..70ebfe81 100644
--- a/ecp5/lpf.cc
+++ b/ecp5/lpf.cc
@@ -134,7 +134,7 @@ bool Arch::apply_lpf(std::string filename, std::istream &in)
if (words.size() > 5)
log_error("unexpected input following LOCATE clause (on line %d)\n", lineno);
if (fnd_cell != cells.end()) {
- fnd_cell->second->attrs[id("LOC")] = strip_quotes(words.at(4));
+ fnd_cell->second->attrs[id_LOC] = strip_quotes(words.at(4));
}
} else if (verb == "IOBUF") {
if (words.size() < 3)
diff --git a/ecp5/main.cc b/ecp5/main.cc
index 1864548b..f143d583 100644
--- a/ecp5/main.cc
+++ b/ecp5/main.cc
@@ -277,7 +277,7 @@ void ECP5CommandHandler::customAfterLoad(Context *ctx)
CellInfo *ci = cell.second.get();
if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_obuf") ||
ci->type == ctx->id("$nextpnr_iobuf")) {
- if (!ci->attrs.count(ctx->id("LOC"))) {
+ if (!ci->attrs.count(id_LOC)) {
if (vm.count("lpf-allow-unconstrained"))
log_warning("IO '%s' is unconstrained in LPF and will be automatically placed\n",
cell.first.c_str(ctx));
diff --git a/ecp5/pack.cc b/ecp5/pack.cc
index 79644d13..d49dbdf3 100644
--- a/ecp5/pack.cc
+++ b/ecp5/pack.cc
@@ -108,11 +108,11 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (is_lut(ctx, ci) || is_pfumx(ctx, ci) || is_l6mux(ctx, ci)) {
- NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
+ NetInfo *znet = ci->ports.at(id_Z).net;
if (znet != nullptr) {
- CellInfo *ff = net_only_drives(ctx, znet, is_ff, ctx->id("DI"), false);
+ CellInfo *ff = net_only_drives(ctx, znet, is_ff, id_DI, false);
// Can't combine preload FF with LUT due to conflict on M
- if (ff != nullptr && get_net_or_empty(ff, ctx->id("M")) == nullptr) {
+ if (ff != nullptr && get_net_or_empty(ff, id_M) == nullptr) {
lutffPairs[ci->name] = ff->name;
fflutPairs[ff->name] = ci->name;
}
@@ -134,13 +134,13 @@ class Ecp5Packer
// Check if a flipflop can be added to a slice
bool can_add_ff_to_slice(CellInfo *slice, CellInfo *ff)
{
- std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK");
- std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR");
+ std::string clkmux = str_or_default(ff->params, id_CLKMUX, "CLK");
+ std::string lsrmux = str_or_default(ff->params, id_LSRMUX, "LSR");
- bool has_dpram = str_or_default(slice->params, ctx->id("MODE"), "LOGIC") == "DPRAM";
+ bool has_dpram = str_or_default(slice->params, id_MODE, "LOGIC") == "DPRAM";
if (has_dpram) {
- std::string wckmux = str_or_default(slice->params, ctx->id("WCKMUX"), "WCK");
- std::string wremux = str_or_default(slice->params, ctx->id("WREMUX"), "WRE");
+ std::string wckmux = str_or_default(slice->params, id_WCKMUX, "WCK");
+ std::string wremux = str_or_default(slice->params, id_WREMUX, "WRE");
if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
return false;
if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
@@ -150,25 +150,22 @@ class Ecp5Packer
bool has_ff1 = get_net_or_empty(slice, id_Q1) != nullptr;
if (!has_ff0 && !has_ff1)
return true;
- if (str_or_default(ff->params, ctx->id("GSR"), "DISABLED") !=
- str_or_default(slice->params, ctx->id("GSR"), "DISABLED"))
+ if (str_or_default(ff->params, id_GSR, "DISABLED") != str_or_default(slice->params, id_GSR, "DISABLED"))
return false;
- if (str_or_default(ff->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
- str_or_default(slice->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
+ if (str_or_default(ff->params, id_SRMODE, "LSR_OVER_CE") !=
+ str_or_default(slice->params, id_SRMODE, "LSR_OVER_CE"))
return false;
- if (str_or_default(ff->params, ctx->id("CEMUX"), "1") != str_or_default(slice->params, ctx->id("CEMUX"), "1"))
+ if (str_or_default(ff->params, id_CEMUX, "1") != str_or_default(slice->params, id_CEMUX, "1"))
return false;
- if (str_or_default(ff->params, ctx->id("LSRMUX"), "LSR") !=
- str_or_default(slice->params, ctx->id("LSRMUX"), "LSR"))
+ if (str_or_default(ff->params, id_LSRMUX, "LSR") != str_or_default(slice->params, id_LSRMUX, "LSR"))
return false;
- if (str_or_default(ff->params, ctx->id("CLKMUX"), "CLK") !=
- str_or_default(slice->params, ctx->id("CLKMUX"), "CLK"))
+ if (str_or_default(ff->params, id_CLKMUX, "CLK") != str_or_default(slice->params, id_CLKMUX, "CLK"))
return false;
- if (net_or_nullptr(ff, ctx->id("CLK")) != net_or_nullptr(slice, ctx->id("CLK")))
+ if (net_or_nullptr(ff, id_CLK) != net_or_nullptr(slice, id_CLK))
return false;
- if (net_or_nullptr(ff, ctx->id("CE")) != net_or_nullptr(slice, ctx->id("CE")))
+ if (net_or_nullptr(ff, id_CE) != net_or_nullptr(slice, id_CE))
return false;
- if (net_or_nullptr(ff, ctx->id("LSR")) != net_or_nullptr(slice, ctx->id("LSR")))
+ if (net_or_nullptr(ff, id_LSR) != net_or_nullptr(slice, id_LSR))
return false;
return true;
}
@@ -185,25 +182,22 @@ class Ecp5Packer
// Return whether two FFs can be packed together in the same slice
bool can_pack_ffs(CellInfo *ff0, CellInfo *ff1)
{
- if (str_or_default(ff0->params, ctx->id("GSR"), "DISABLED") !=
- str_or_default(ff1->params, ctx->id("GSR"), "DISABLED"))
+ if (str_or_default(ff0->params, id_GSR, "DISABLED") != str_or_default(ff1->params, id_GSR, "DISABLED"))
return false;
- if (str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
- str_or_default(ff1->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
+ if (str_or_default(ff0->params, id_SRMODE, "LSR_OVER_CE") !=
+ str_or_default(ff1->params, id_SRMODE, "LSR_OVER_CE"))
return false;
- if (str_or_default(ff0->params, ctx->id("CEMUX"), "1") != str_or_default(ff1->params, ctx->id("CEMUX"), "1"))
+ if (str_or_default(ff0->params, id_CEMUX, "1") != str_or_default(ff1->params, id_CEMUX, "1"))
return false;
- if (str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR") !=
- str_or_default(ff1->params, ctx->id("LSRMUX"), "LSR"))
+ if (str_or_default(ff0->params, id_LSRMUX, "LSR") != str_or_default(ff1->params, id_LSRMUX, "LSR"))
return false;
- if (str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK") !=
- str_or_default(ff1->params, ctx->id("CLKMUX"), "CLK"))
+ if (str_or_default(ff0->params, id_CLKMUX, "CLK") != str_or_default(ff1->params, id_CLKMUX, "CLK"))
return false;
- if (net_or_nullptr(ff0, ctx->id("CLK")) != net_or_nullptr(ff1, ctx->id("CLK")))
+ if (net_or_nullptr(ff0, id_CLK) != net_or_nullptr(ff1, id_CLK))
return false;
- if (net_or_nullptr(ff0, ctx->id("CE")) != net_or_nullptr(ff1, ctx->id("CE")))
+ if (net_or_nullptr(ff0, id_CE) != net_or_nullptr(ff1, id_CE))
return false;
- if (net_or_nullptr(ff0, ctx->id("LSR")) != net_or_nullptr(ff1, ctx->id("LSR")))
+ if (net_or_nullptr(ff0, id_LSR) != net_or_nullptr(ff1, id_LSR))
return false;
return true;
}
@@ -212,18 +206,16 @@ class Ecp5Packer
bool can_add_ff_to_tile(const std::vector<CellInfo *> &tile_ffs, CellInfo *ff0)
{
for (const auto &existing : tile_ffs) {
- if (net_or_nullptr(existing, ctx->id("CLK")) != net_or_nullptr(ff0, ctx->id("CLK")))
+ if (net_or_nullptr(existing, id_CLK) != net_or_nullptr(ff0, id_CLK))
return false;
- if (net_or_nullptr(existing, ctx->id("LSR")) != net_or_nullptr(ff0, ctx->id("LSR")))
+ if (net_or_nullptr(existing, id_LSR) != net_or_nullptr(ff0, id_LSR))
return false;
- if (str_or_default(existing->params, ctx->id("CLKMUX"), "CLK") !=
- str_or_default(ff0->params, ctx->id("CLKMUX"), "CLK"))
+ if (str_or_default(existing->params, id_CLKMUX, "CLK") != str_or_default(ff0->params, id_CLKMUX, "CLK"))
return false;
- if (str_or_default(existing->params, ctx->id("LSRMUX"), "LSR") !=
- str_or_default(ff0->params, ctx->id("LSRMUX"), "LSR"))
+ if (str_or_default(existing->params, id_LSRMUX, "LSR") != str_or_default(ff0->params, id_LSRMUX, "LSR"))
return false;
- if (str_or_default(existing->params, ctx->id("SRMODE"), "LSR_OVER_CE") !=
- str_or_default(ff0->params, ctx->id("SRMODE"), "LSR_OVER_CE"))
+ if (str_or_default(existing->params, id_SRMODE, "LSR_OVER_CE") !=
+ str_or_default(ff0->params, id_SRMODE, "LSR_OVER_CE"))
return false;
}
return true;
@@ -232,14 +224,14 @@ class Ecp5Packer
// Return true if a FF can be added to a DPRAM slice
bool can_pack_ff_dram(CellInfo *dpram, CellInfo *ff)
{
- if (get_net_or_empty(ff, ctx->id("M")) != nullptr)
+ if (get_net_or_empty(ff, id_M) != nullptr)
return false; // skip PRLD FFs due to M/DI conflict
- std::string wckmux = str_or_default(dpram->params, ctx->id("WCKMUX"), "WCK");
- std::string clkmux = str_or_default(ff->params, ctx->id("CLKMUX"), "CLK");
+ std::string wckmux = str_or_default(dpram->params, id_WCKMUX, "WCK");
+ std::string clkmux = str_or_default(ff->params, id_CLKMUX, "CLK");
if (wckmux != clkmux && !(wckmux == "WCK" && clkmux == "CLK"))
return false;
- std::string wremux = str_or_default(dpram->params, ctx->id("WREMUX"), "WRE");
- std::string lsrmux = str_or_default(ff->params, ctx->id("LSRMUX"), "LSR");
+ std::string wremux = str_or_default(dpram->params, id_WREMUX, "WRE");
+ std::string lsrmux = str_or_default(ff->params, id_LSRMUX, "LSR");
if (wremux != lsrmux && !(wremux == "WRE" && lsrmux == "LSR"))
return false;
return true;
@@ -264,7 +256,7 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (is_lut(ctx, ci) && procdLuts.find(cell.first) == procdLuts.end()) {
- NetInfo *znet = ci->ports.at(ctx->id("Z")).net;
+ NetInfo *znet = ci->ports.at(id_Z).net;
std::vector<NetInfo *> inpnets;
if (znet != nullptr) {
for (auto user : znet->users) {
@@ -284,7 +276,7 @@ class Ecp5Packer
}
}
if (lutffPairs.find(ci->name) != lutffPairs.end()) {
- NetInfo *qnet = ctx->cells.at(lutffPairs[ci->name])->ports.at(ctx->id("Q")).net;
+ NetInfo *qnet = ctx->cells.at(lutffPairs[ci->name])->ports.at(id_Q).net;
if (qnet != nullptr) {
for (auto user : qnet->users) {
if (is_lut(ctx, user.cell) && user.cell != ci &&
@@ -309,7 +301,7 @@ class Ecp5Packer
NetInfo *innet = ci->ports.at(ctx->id(inp)).net;
if (innet != nullptr && innet->driver.cell != nullptr) {
CellInfo *drv = innet->driver.cell;
- if (is_lut(ctx, drv) && drv != ci && innet->driver.port == ctx->id("Z")) {
+ if (is_lut(ctx, drv) && drv != ci && innet->driver.port == id_Z) {
if (procdLuts.find(drv->name) == procdLuts.end()) {
if (can_pack_lutff(ci->name, drv->name)) {
procdLuts.insert(ci->name);
@@ -318,7 +310,7 @@ class Ecp5Packer
goto paired_inlut;
}
}
- } else if (is_ff(ctx, drv) && innet->driver.port == ctx->id("Q")) {
+ } else if (is_ff(ctx, drv) && innet->driver.port == id_Q) {
auto fflut = fflutPairs.find(drv->name);
if (fflut != fflutPairs.end() && fflut->second != ci->name &&
procdLuts.find(fflut->second) == procdLuts.end()) {
@@ -336,7 +328,7 @@ class Ecp5Packer
// Pack LUTs feeding the same CCU2, RAM or DFF into a SLICE
if (znet != nullptr && znet->users.size() < 10) {
for (auto user : znet->users) {
- if (is_lc(ctx, user.cell) || user.cell->type == ctx->id("DP16KD") || is_ff(ctx, user.cell)) {
+ if (is_lc(ctx, user.cell) || user.cell->type == id_DP16KD || is_ff(ctx, user.cell)) {
for (auto port : user.cell->ports) {
if (port.second.type != PORT_IN || port.second.net == nullptr ||
port.second.net == znet)
@@ -449,12 +441,12 @@ class Ecp5Packer
NetInfo *ionet = nullptr;
PortRef tp;
if (ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) {
- ionet = ci->ports.at(ctx->id("O")).net;
- trio = net_only_drives(ctx, ionet, is_trellis_io, ctx->id("B"), true, ci);
+ ionet = ci->ports.at(id_O).net;
+ trio = net_only_drives(ctx, ionet, is_trellis_io, id_B, true, ci);
} else if (ci->type == ctx->id("$nextpnr_obuf")) {
- ionet = ci->ports.at(ctx->id("I")).net;
- trio = net_only_drives(ctx, ci->ports.at(ctx->id("I")).net, is_trellis_io, ctx->id("B"), true, ci);
+ ionet = ci->ports.at(id_I).net;
+ trio = net_only_drives(ctx, ci->ports.at(id_I).net, is_trellis_io, id_B, true, ci);
}
if (bool_or_default(ctx->settings, ctx->id("arch.ooc"))) {
// No IO buffer insertion in out-of-context mode, just remove the nextpnr buffer
@@ -466,18 +458,18 @@ class Ecp5Packer
log_info("%s feeds TRELLIS_IO %s, removing %s %s.\n", ci->name.c_str(ctx), trio->name.c_str(ctx),
ci->type.c_str(ctx), ci->name.c_str(ctx));
- NetInfo *net = trio->ports.at(ctx->id("B")).net;
+ NetInfo *net = trio->ports.at(id_B).net;
if (((ci->type == ctx->id("$nextpnr_ibuf") || ci->type == ctx->id("$nextpnr_iobuf")) &&
net->users.size() > 1) ||
(ci->type == ctx->id("$nextpnr_obuf") &&
(net->users.size() > 2 || net->driver.cell != nullptr)) ||
- (ci->type == ctx->id("$nextpnr_iobuf") && ci->ports.at(ctx->id("I")).net != nullptr &&
- ci->ports.at(ctx->id("I")).net->driver.cell != nullptr))
+ (ci->type == ctx->id("$nextpnr_iobuf") && ci->ports.at(id_I).net != nullptr &&
+ ci->ports.at(id_I).net->driver.cell != nullptr))
log_error("Pin B of %s '%s' connected to more than a single top level IO.\n",
trio->type.c_str(ctx), trio->name.c_str(ctx));
if (net != nullptr) {
- if (net->clkconstr != nullptr && trio->ports.count(ctx->id("O"))) {
- NetInfo *onet = trio->ports.at(ctx->id("O")).net;
+ if (net->clkconstr != nullptr && trio->ports.count(id_O)) {
+ NetInfo *onet = trio->ports.at(id_O).net;
if (onet != nullptr && !onet->clkconstr) {
// Move clock constraint from IO pad to input buffer output
std::swap(net->clkconstr, onet->clkconstr);
@@ -492,7 +484,7 @@ class Ecp5Packer
tp.cell->ports.at(tp.port).net = nullptr;
}
if (ci->type == ctx->id("$nextpnr_iobuf")) {
- NetInfo *net2 = ci->ports.at(ctx->id("I")).net;
+ NetInfo *net2 = ci->ports.at(id_I).net;
if (net2 != nullptr) {
ctx->nets.erase(net2->name);
}
@@ -500,7 +492,7 @@ class Ecp5Packer
} else {
// Create a TRELLIS_IO buffer
std::unique_ptr<CellInfo> tr_cell =
- create_ecp5_cell(ctx, ctx->id("TRELLIS_IO"), ci->name.str(ctx) + "$tr_io");
+ create_ecp5_cell(ctx, id_TRELLIS_IO, ci->name.str(ctx) + "$tr_io");
nxio_to_tr(ctx, ci, tr_cell.get(), new_cells, packed_cells);
new_cells.push_back(std::move(tr_cell));
trio = new_cells.back().get();
@@ -512,7 +504,7 @@ class Ecp5Packer
for (const auto &attr : ci->attrs)
trio->attrs[attr.first] = attr.second;
- auto loc_attr = trio->attrs.find(ctx->id("LOC"));
+ auto loc_attr = trio->attrs.find(id_LOC);
if (loc_attr != trio->attrs.end()) {
std::string pin = loc_attr->second.as_string();
BelId pinBel = ctx->get_package_pin_bel(pin);
@@ -523,7 +515,7 @@ class Ecp5Packer
log_info("pin '%s' constrained to Bel '%s'.\n", trio->name.c_str(ctx),
ctx->nameOfBel(pinBel));
}
- trio->attrs[ctx->id("BEL")] = ctx->getBelName(pinBel).str(ctx);
+ trio->attrs[id_BEL] = ctx->getBelName(pinBel).str(ctx);
}
}
}
@@ -539,35 +531,33 @@ class Ecp5Packer
CellInfo *ci = cell.second.get();
if (is_pfumx(ctx, ci)) {
std::unique_ptr<CellInfo> packed =
- create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
- NetInfo *f0 = ci->ports.at(ctx->id("BLUT")).net;
+ create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_SLICE");
+ NetInfo *f0 = ci->ports.at(id_BLUT).net;
if (f0 == nullptr)
log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
- NetInfo *f1 = ci->ports.at(ctx->id("ALUT")).net;
+ NetInfo *f1 = ci->ports.at(id_ALUT).net;
if (f1 == nullptr)
log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
- CellInfo *lut0 = net_driven_by(ctx, f0, is_lut, ctx->id("Z"));
- CellInfo *lut1 = net_driven_by(ctx, f1, is_lut, ctx->id("Z"));
+ CellInfo *lut0 = net_driven_by(ctx, f0, is_lut, id_Z);
+ CellInfo *lut1 = net_driven_by(ctx, f1, is_lut, id_Z);
if (lut0 == nullptr)
log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
if (lut1 == nullptr)
log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
if (ctx->verbose)
log_info(" mux '%s' forms part of a LUT5\n", cell.first.c_str(ctx));
- replace_port(lut0, ctx->id("A"), packed.get(), ctx->id("A0"));
- replace_port(lut0, ctx->id("B"), packed.get(), ctx->id("B0"));
- replace_port(lut0, ctx->id("C"), packed.get(), ctx->id("C0"));
- replace_port(lut0, ctx->id("D"), packed.get(), ctx->id("D0"));
- replace_port(lut1, ctx->id("A"), packed.get(), ctx->id("A1"));
- replace_port(lut1, ctx->id("B"), packed.get(), ctx->id("B1"));
- replace_port(lut1, ctx->id("C"), packed.get(), ctx->id("C1"));
- replace_port(lut1, ctx->id("D"), packed.get(), ctx->id("D1"));
- replace_port(ci, ctx->id("C0"), packed.get(), ctx->id("M0"));
- replace_port(ci, ctx->id("Z"), packed.get(), ctx->id("OFX0"));
- packed->params[ctx->id("LUT0_INITVAL")] =
- get_or_default(lut0->params, ctx->id("INIT"), Property(0, 16));
- packed->params[ctx->id("LUT1_INITVAL")] =
- get_or_default(lut1->params, ctx->id("INIT"), Property(0, 16));
+ replace_port(lut0, id_A, packed.get(), id_A0);
+ replace_port(lut0, id_B, packed.get(), id_B0);
+ replace_port(lut0, id_C, packed.get(), id_C0);
+ replace_port(lut0, id_D, packed.get(), id_D0);
+ replace_port(lut1, id_A, packed.get(), id_A1);
+ replace_port(lut1, id_B, packed.get(), id_B1);
+ replace_port(lut1, id_C, packed.get(), id_C1);
+ replace_port(lut1, id_D, packed.get(), id_D1);
+ replace_port(ci, id_C0, packed.get(), id_M0);
+ replace_port(ci, id_Z, packed.get(), id_OFX0);
+ packed->params[id_LUT0_INITVAL] = get_or_default(lut0->params, id_INIT, Property(0, 16));
+ packed->params[id_LUT1_INITVAL] = get_or_default(lut1->params, id_INIT, Property(0, 16));
ctx->nets.erase(f0->name);
ctx->nets.erase(f1->name);
@@ -595,17 +585,16 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (is_l6mux(ctx, ci)) {
- NetInfo *ofx0_0 = ci->ports.at(ctx->id("D0")).net;
+ NetInfo *ofx0_0 = ci->ports.at(id_D0).net;
if (ofx0_0 == nullptr)
log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
- NetInfo *ofx0_1 = ci->ports.at(ctx->id("D1")).net;
+ NetInfo *ofx0_1 = ci->ports.at(id_D1).net;
if (ofx0_1 == nullptr)
log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
- CellInfo *slice0 = net_driven_by(ctx, ofx0_0, is_lc, ctx->id("OFX0"));
- CellInfo *slice1 = net_driven_by(ctx, ofx0_1, is_lc, ctx->id("OFX0"));
+ CellInfo *slice0 = net_driven_by(ctx, ofx0_0, is_lc, id_OFX0);
+ CellInfo *slice1 = net_driven_by(ctx, ofx0_1, is_lc, id_OFX0);
if (slice0 == nullptr) {
- if (!net_driven_by(ctx, ofx0_0, is_l6mux, ctx->id("Z")) &&
- !net_driven_by(ctx, ofx0_0, is_lc, ctx->id("OFX1")))
+ if (!net_driven_by(ctx, ofx0_0, is_l6mux, id_Z) && !net_driven_by(ctx, ofx0_0, is_lc, id_OFX1))
log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
"('%s.%s')\n",
ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
@@ -613,8 +602,7 @@ class Ecp5Packer
continue;
}
if (slice1 == nullptr) {
- if (!net_driven_by(ctx, ofx0_1, is_l6mux, ctx->id("Z")) &&
- !net_driven_by(ctx, ofx0_1, is_lc, ctx->id("OFX1")))
+ if (!net_driven_by(ctx, ofx0_1, is_l6mux, id_Z) && !net_driven_by(ctx, ofx0_1, is_lc, id_OFX1))
log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
"('%s.%s')\n",
ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
@@ -623,10 +611,10 @@ class Ecp5Packer
}
if (ctx->verbose)
log_info(" mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
- replace_port(ci, ctx->id("D0"), slice1, id_FXA);
- replace_port(ci, ctx->id("D1"), slice1, id_FXB);
- replace_port(ci, ctx->id("SD"), slice1, id_M1);
- replace_port(ci, ctx->id("Z"), slice1, id_OFX1);
+ replace_port(ci, id_D0, slice1, id_FXA);
+ replace_port(ci, id_D1, slice1, id_FXB);
+ replace_port(ci, id_SD, slice1, id_M1);
+ replace_port(ci, id_Z, slice1, id_OFX1);
slice0->constr_z = 1;
slice0->constr_x = 0;
slice0->constr_y = 0;
@@ -653,14 +641,14 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (is_l6mux(ctx, ci)) {
- NetInfo *ofx1_0 = ci->ports.at(ctx->id("D0")).net;
+ NetInfo *ofx1_0 = ci->ports.at(id_D0).net;
if (ofx1_0 == nullptr)
log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
- NetInfo *ofx1_1 = ci->ports.at(ctx->id("D1")).net;
+ NetInfo *ofx1_1 = ci->ports.at(id_D1).net;
if (ofx1_1 == nullptr)
log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
- CellInfo *slice1 = net_driven_by(ctx, ofx1_0, is_lc, ctx->id("OFX1"));
- CellInfo *slice3 = net_driven_by(ctx, ofx1_1, is_lc, ctx->id("OFX1"));
+ CellInfo *slice1 = net_driven_by(ctx, ofx1_0, is_lc, id_OFX1);
+ CellInfo *slice3 = net_driven_by(ctx, ofx1_1, is_lc, id_OFX1);
if (slice1 == nullptr)
log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX ('%s.%s')\n",
ci->name.c_str(ctx), ofx1_0->driver.cell->name.c_str(ctx),
@@ -677,8 +665,8 @@ class Ecp5Packer
if (fxa_1 == nullptr)
log_error("SLICE '%s' has disconnected port 'FXA'\n", slice3->name.c_str(ctx));
- CellInfo *slice0 = net_driven_by(ctx, fxa_0, is_lc, ctx->id("OFX0"));
- CellInfo *slice2 = net_driven_by(ctx, fxa_1, is_lc, ctx->id("OFX0"));
+ CellInfo *slice0 = net_driven_by(ctx, fxa_0, is_lc, id_OFX0);
+ CellInfo *slice2 = net_driven_by(ctx, fxa_1, is_lc, id_OFX0);
if (slice0 == nullptr)
log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
slice1->name.c_str(ctx), fxa_0->driver.cell->name.c_str(ctx),
@@ -688,10 +676,10 @@ class Ecp5Packer
slice3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
fxa_1->driver.port.c_str(ctx));
- replace_port(ci, ctx->id("D0"), slice2, id_FXA);
- replace_port(ci, ctx->id("D1"), slice2, id_FXB);
- replace_port(ci, ctx->id("SD"), slice2, id_M1);
- replace_port(ci, ctx->id("Z"), slice2, id_OFX1);
+ replace_port(ci, id_D0, slice2, id_FXA);
+ replace_port(ci, id_D1, slice2, id_FXB);
+ replace_port(ci, id_SD, slice2, id_M1);
+ replace_port(ci, id_Z, slice2, id_OFX1);
for (auto slice : {slice0, slice1, slice2, slice3}) {
slice->constr_children.clear();
@@ -747,12 +735,12 @@ class Ecp5Packer
// Create a feed in to the carry chain
CellInfo *make_carry_feed_in(NetInfo *carry, PortRef chain_in)
{
- std::unique_ptr<CellInfo> feedin = create_ecp5_cell(ctx, ctx->id("CCU2C"));
+ std::unique_ptr<CellInfo> feedin = create_ecp5_cell(ctx, id_CCU2C);
- feedin->params[ctx->id("INIT0")] = Property(10, 16); // LUT4 = 0; LUT2 = A
- feedin->params[ctx->id("INIT1")] = Property(65535, 16);
- feedin->params[ctx->id("INJECT1_0")] = std::string("NO");
- feedin->params[ctx->id("INJECT1_1")] = std::string("YES");
+ feedin->params[id_INIT0] = Property(10, 16); // LUT4 = 0; LUT2 = A
+ feedin->params[id_INIT1] = Property(65535, 16);
+ feedin->params[id_INJECT1_0] = std::string("NO");
+ feedin->params[id_INJECT1_1] = std::string("YES");
carry->users.erase(std::remove_if(carry->users.begin(), carry->users.end(),
[chain_in](const PortRef &user) {
@@ -762,7 +750,7 @@ class Ecp5Packer
connect_port(ctx, carry, feedin.get(), id_A0);
NetInfo *new_carry = ctx->createNet(ctx->id(feedin->name.str(ctx) + "$COUT"));
- connect_port(ctx, new_carry, feedin.get(), ctx->id("COUT"));
+ connect_port(ctx, new_carry, feedin.get(), id_COUT);
chain_in.cell->ports[chain_in.port].net = nullptr;
connect_port(ctx, new_carry, chain_in.cell, chain_in.port);
@@ -775,21 +763,21 @@ class Ecp5Packer
// Create a feed out and loop through from the carry chain
CellInfo *make_carry_feed_out(NetInfo *carry, boost::optional<PortRef> chain_next = boost::optional<PortRef>())
{
- std::unique_ptr<CellInfo> feedout = create_ecp5_cell(ctx, ctx->id("CCU2C"));
+ std::unique_ptr<CellInfo> feedout = create_ecp5_cell(ctx, id_CCU2C);
- feedout->params[ctx->id("INIT0")] = Property(0, 16);
- feedout->params[ctx->id("INIT1")] = Property(10, 16); // LUT4 = 0; LUT2 = A
- feedout->params[ctx->id("INJECT1_0")] = std::string("NO");
- feedout->params[ctx->id("INJECT1_1")] = std::string("NO");
+ feedout->params[id_INIT0] = Property(0, 16);
+ feedout->params[id_INIT1] = Property(10, 16); // LUT4 = 0; LUT2 = A
+ feedout->params[id_INJECT1_0] = std::string("NO");
+ feedout->params[id_INJECT1_1] = std::string("NO");
PortRef carry_drv = carry->driver;
carry->driver.cell = nullptr;
- connect_port(ctx, carry, feedout.get(), ctx->id("S0"));
+ connect_port(ctx, carry, feedout.get(), id_S0);
NetInfo *new_cin = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$CIN"));
new_cin->driver = carry_drv;
carry_drv.cell->ports.at(carry_drv.port).net = new_cin;
- connect_port(ctx, new_cin, feedout.get(), ctx->id("CIN"));
+ connect_port(ctx, new_cin, feedout.get(), id_CIN);
if (chain_next) {
// Loop back into LUT4_1 for feedthrough
@@ -802,7 +790,7 @@ class Ecp5Packer
carry->users.end());
NetInfo *new_cout = ctx->createNet(ctx->id(feedout->name.str(ctx) + "$COUT"));
- connect_port(ctx, new_cout, feedout.get(), ctx->id("COUT"));
+ connect_port(ctx, new_cout, feedout.get(), id_COUT);
chain_next->cell->ports[chain_next->port].net = nullptr;
connect_port(ctx, new_cout, chain_next->cell, chain_next->port);
@@ -827,23 +815,23 @@ class Ecp5Packer
if (start_of_chain) {
chains.emplace_back();
start_of_chain = false;
- if (cell->ports.at(ctx->id("CIN")).net) {
+ if (cell->ports.at(id_CIN).net) {
// CIN is not constant and not part of a chain. Must feed in from fabric
PortRef inport;
inport.cell = cell;
- inport.port = ctx->id("CIN");
- CellInfo *feedin = make_carry_feed_in(cell->ports.at(ctx->id("CIN")).net, inport);
+ inport.port = id_CIN;
+ CellInfo *feedin = make_carry_feed_in(cell->ports.at(id_CIN).net, inport);
chains.back().cells.push_back(feedin);
}
}
chains.back().cells.push_back(cell);
bool split_chain = int(chains.back().cells.size()) > max_length;
if (split_chain) {
- CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net);
+ CellInfo *passout = make_carry_feed_out(cell->ports.at(id_COUT).net);
chains.back().cells.back() = passout;
start_of_chain = true;
} else {
- NetInfo *carry_net = cell->ports.at(ctx->id("COUT")).net;
+ NetInfo *carry_net = cell->ports.at(id_COUT).net;
bool at_end = (curr_cell == carryc.cells.end() - 1);
if (carry_net != nullptr && (carry_net->users.size() > 1 || at_end)) {
boost::optional<PortRef> nextport;
@@ -851,10 +839,10 @@ class Ecp5Packer
auto next_cell = *(curr_cell + 1);
PortRef nextpr;
nextpr.cell = next_cell;
- nextpr.port = ctx->id("CIN");
+ nextpr.port = id_CIN;
nextport = nextpr;
}
- CellInfo *passout = make_carry_feed_out(cell->ports.at(ctx->id("COUT")).net, nextport);
+ CellInfo *passout = make_carry_feed_out(cell->ports.at(id_COUT).net, nextport);
chains.back().cells.push_back(passout);
}
++curr_cell;
@@ -871,10 +859,10 @@ class Ecp5Packer
auto carry_chains = find_chains(
ctx, [](const Context *ctx, const CellInfo *cell) { return is_carry(ctx, cell); },
[](const Context *ctx, const CellInfo *cell) {
- return net_driven_by(ctx, cell->ports.at(ctx->id("CIN")).net, is_carry, ctx->id("COUT"));
+ return net_driven_by(ctx, cell->ports.at(id_CIN).net, is_carry, id_COUT);
},
[](const Context *ctx, const CellInfo *cell) {
- return net_only_drives(ctx, cell->ports.at(ctx->id("COUT")).net, is_carry, ctx->id("CIN"), false);
+ return net_only_drives(ctx, cell->ports.at(id_COUT).net, is_carry, id_CIN, false);
},
1);
std::vector<CellChain> all_chains;
@@ -905,14 +893,14 @@ class Ecp5Packer
if (cell_count % 4 == 0)
tile_ffs.clear();
std::unique_ptr<CellInfo> slice =
- create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), cell->name.str(ctx) + "$CCU2_SLICE");
+ create_ecp5_cell(ctx, id_TRELLIS_SLICE, cell->name.str(ctx) + "$CCU2_SLICE");
ccu2c_to_slice(ctx, cell, slice.get());
CellInfo *ff0 = nullptr;
- NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
+ NetInfo *f0net = slice->ports.at(id_F0).net;
if (f0net != nullptr) {
- ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
+ ff0 = net_only_drives(ctx, f0net, is_ff, id_DI, false);
if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
ff_packing.push_back(std::make_tuple(ff0, slice.get(), 0));
tile_ffs.push_back(ff0);
@@ -921,9 +909,9 @@ class Ecp5Packer
}
CellInfo *ff1 = nullptr;
- NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
+ NetInfo *f1net = slice->ports.at(id_F1).net;
if (f1net != nullptr) {
- ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
+ ff1 = net_only_drives(ctx, f1net, is_ff, id_DI, false);
if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
can_add_ff_to_tile(tile_ffs, ff1)) {
ff_packing.push_back(std::make_tuple(ff1, slice.get(), 1));
@@ -969,16 +957,16 @@ class Ecp5Packer
// Create RAMW slice
std::unique_ptr<CellInfo> ramw_slice =
- create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$RAMW_SLICE");
+ create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "$RAMW_SLICE");
dram_to_ramw(ctx, ci, ramw_slice.get());
// Create actual RAM slices
std::unique_ptr<CellInfo> ram0_slice =
- create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM0_SLICE");
+ create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "$DPRAM0_SLICE");
dram_to_ram_slice(ctx, ci, ram0_slice.get(), ramw_slice.get(), 0);
std::unique_ptr<CellInfo> ram1_slice =
- create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "$DPRAM1_SLICE");
+ create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "$DPRAM1_SLICE");
dram_to_ram_slice(ctx, ci, ram1_slice.get(), ramw_slice.get(), 1);
// Disconnect ports of original cell after packing
@@ -995,9 +983,9 @@ class Ecp5Packer
std::vector<CellInfo *> tile_ffs;
for (auto slice : {ram0_slice.get(), ram1_slice.get()}) {
CellInfo *ff0 = nullptr;
- NetInfo *f0net = slice->ports.at(ctx->id("F0")).net;
+ NetInfo *f0net = slice->ports.at(id_F0).net;
if (f0net != nullptr) {
- ff0 = net_only_drives(ctx, f0net, is_ff, ctx->id("DI"), false);
+ ff0 = net_only_drives(ctx, f0net, is_ff, id_DI, false);
if (ff0 != nullptr && can_add_ff_to_tile(tile_ffs, ff0)) {
if (can_pack_ff_dram(slice, ff0)) {
ff_packing.push_back(std::make_tuple(ff0, slice, 0));
@@ -1008,9 +996,9 @@ class Ecp5Packer
}
CellInfo *ff1 = nullptr;
- NetInfo *f1net = slice->ports.at(ctx->id("F1")).net;
+ NetInfo *f1net = slice->ports.at(id_F1).net;
if (f1net != nullptr) {
- ff1 = net_only_drives(ctx, f1net, is_ff, ctx->id("DI"), false);
+ ff1 = net_only_drives(ctx, f1net, is_ff, id_DI, false);
if (ff1 != nullptr && (ff0 == nullptr || can_pack_ffs(ff0, ff1)) &&
can_add_ff_to_tile(tile_ffs, ff1)) {
if (can_pack_ff_dram(slice, ff1)) {
@@ -1060,8 +1048,7 @@ class Ecp5Packer
for (auto pair : lutPairs) {
CellInfo *lut0 = ctx->cells.at(pair.first).get();
CellInfo *lut1 = ctx->cells.at(pair.second).get();
- std::unique_ptr<CellInfo> slice =
- create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), lut0->name.str(ctx) + "_SLICE");
+ std::unique_ptr<CellInfo> slice = create_ecp5_cell(ctx, id_TRELLIS_SLICE, lut0->name.str(ctx) + "_SLICE");
lut_to_slice(ctx, lut0, slice.get(), 0);
lut_to_slice(ctx, lut1, slice.get(), 1);
@@ -1099,8 +1086,7 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (is_lut(ctx, ci)) {
- std::unique_ptr<CellInfo> slice =
- create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
+ std::unique_ptr<CellInfo> slice = create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_SLICE");
lut_to_slice(ctx, ci, slice.get(), 1);
auto ff = lutffPairs.find(ci->name);
@@ -1173,7 +1159,7 @@ class Ecp5Packer
CellInfo *ci = cell.second.get();
if (is_ff(ctx, ci)) {
bool pack_dense = used_slices > (dense_pack_mode_thresh * available_slices);
- bool requires_m = get_net_or_empty(ci, ctx->id("M")) != nullptr;
+ bool requires_m = get_net_or_empty(ci, id_M) != nullptr;
if (pack_dense && !requires_m) {
// If dense packing threshold exceeded; always try and pack the FF into an existing slice
// Find a SLICE with space "near" the flipflop in the netlist
@@ -1222,8 +1208,7 @@ class Ecp5Packer
}
}
- std::unique_ptr<CellInfo> slice =
- create_ecp5_cell(ctx, ctx->id("TRELLIS_SLICE"), ci->name.str(ctx) + "_SLICE");
+ std::unique_ptr<CellInfo> slice = create_ecp5_cell(ctx, id_TRELLIS_SLICE, ci->name.str(ctx) + "_SLICE");
ff_to_slice(ctx, ci, slice.get(), 0, false);
new_cells.push_back(std::move(slice));
++used_slices;
@@ -1252,9 +1237,9 @@ class Ecp5Packer
void set_lut_input_constant(CellInfo *cell, IdString input, bool value)
{
int index = std::string("ABCD").find(input.str(ctx));
- int init = int_or_default(cell->params, ctx->id("INIT"));
+ int init = int_or_default(cell->params, id_INIT);
int new_init = make_init_with_const_input(init, index, value);
- cell->params[ctx->id("INIT")] = Property(new_init, 16);
+ cell->params[id_INIT] = Property(new_init, 16);
cell->ports.at(input).net = nullptr;
}
@@ -1275,8 +1260,7 @@ class Ecp5Packer
return true; // disconnected port is high
if (cell->ports.at(input).net == nullptr || cell->ports.at(input).net->name == ctx->id("$PACKER_VCC_NET"))
return true; // disconnected or tied-high port
- if (cell->ports.at(input).net->driver.cell != nullptr &&
- cell->ports.at(input).net->driver.cell->type == ctx->id("VCC"))
+ if (cell->ports.at(input).net->driver.cell != nullptr && cell->ports.at(input).net->driver.cell->type == id_VCC)
return true; // pre-pack high
return false;
}
@@ -1292,8 +1276,8 @@ class Ecp5Packer
log_info("%s user %s\n", orig->name.c_str(ctx), uc->name.c_str(ctx));
if (is_lut(ctx, uc)) {
set_lut_input_constant(uc, user.port, constval);
- } else if (is_ff(ctx, uc) && user.port == ctx->id("CE")) {
- uc->params[ctx->id("CEMUX")] = std::string(constval ? "1" : "0");
+ } else if (is_ff(ctx, uc) && user.port == id_CE) {
+ uc->params[id_CEMUX] = std::string(constval ? "1" : "0");
uc->ports[user.port].net = nullptr;
} else if (is_carry(ctx, uc)) {
if (constval &&
@@ -1326,9 +1310,9 @@ class Ecp5Packer
uc->ports[user.port].net = constnet;
constnet->users.push_back(user);
}
- } else if (is_ff(ctx, uc) && user.port == ctx->id("LSR") &&
- ((!constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "LSR") ||
- (constval && str_or_default(uc->params, ctx->id("LSRMUX"), "LSR") == "INV"))) {
+ } else if (is_ff(ctx, uc) && user.port == id_LSR &&
+ ((!constval && str_or_default(uc->params, id_LSRMUX, "LSR") == "LSR") ||
+ (constval && str_or_default(uc->params, id_LSRMUX, "LSR") == "INV"))) {
uc->ports[user.port].net = nullptr;
} else if (uc->type == id_DP16KD) {
if (user.port == id_CLKA || user.port == id_CLKB || user.port == id_RSTA || user.port == id_RSTB ||
@@ -1371,19 +1355,19 @@ class Ecp5Packer
{
log_info("Packing constants..\n");
- std::unique_ptr<CellInfo> gnd_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_GND");
- gnd_cell->params[ctx->id("INIT")] = Property(0, 16);
+ std::unique_ptr<CellInfo> gnd_cell = create_ecp5_cell(ctx, id_LUT4, "$PACKER_GND");
+ gnd_cell->params[id_INIT] = Property(0, 16);
auto gnd_net = std::make_unique<NetInfo>(ctx->id("$PACKER_GND_NET"));
gnd_net->driver.cell = gnd_cell.get();
- gnd_net->driver.port = ctx->id("Z");
- gnd_cell->ports.at(ctx->id("Z")).net = gnd_net.get();
+ gnd_net->driver.port = id_Z;
+ gnd_cell->ports.at(id_Z).net = gnd_net.get();
- std::unique_ptr<CellInfo> vcc_cell = create_ecp5_cell(ctx, ctx->id("LUT4"), "$PACKER_VCC");
- vcc_cell->params[ctx->id("INIT")] = Property(65535, 16);
+ std::unique_ptr<CellInfo> vcc_cell = create_ecp5_cell(ctx, id_LUT4, "$PACKER_VCC");
+ vcc_cell->params[id_INIT] = Property(65535, 16);
auto vcc_net = std::make_unique<NetInfo>(ctx->id("$PACKER_VCC_NET"));
vcc_net->driver.cell = vcc_cell.get();
- vcc_net->driver.port = ctx->id("Z");
- vcc_cell->ports.at(ctx->id("Z")).net = vcc_net.get();
+ vcc_net->driver.port = id_Z;
+ vcc_cell->ports.at(id_Z).net = vcc_net.get();
std::vector<IdString> dead_nets;
@@ -1391,13 +1375,13 @@ class Ecp5Packer
for (auto &net : ctx->nets) {
NetInfo *ni = net.second.get();
- if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("GND")) {
+ if (ni->driver.cell != nullptr && ni->driver.cell->type == id_GND) {
IdString drv_cell = ni->driver.cell->name;
set_net_constant(ctx, ni, gnd_net.get(), false);
gnd_used = true;
dead_nets.push_back(net.first);
ctx->cells.erase(drv_cell);
- } else if (ni->driver.cell != nullptr && ni->driver.cell->type == ctx->id("VCC")) {
+ } else if (ni->driver.cell != nullptr && ni->driver.cell->type == id_VCC) {
IdString drv_cell = ni->driver.cell->name;
set_net_constant(ctx, ni, vcc_net.get(), true);
vcc_used = true;
@@ -1450,9 +1434,9 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
// Convert 36-bit PDP RAMs to regular 18-bit DP ones that match the Bel
- if (ci->type == ctx->id("PDPW16KD")) {
- ci->params[ctx->id("DATA_WIDTH_A")] = 36; // force PDP mode
- ci->params.erase(ctx->id("DATA_WIDTH_W"));
+ if (ci->type == id_PDPW16KD) {
+ ci->params[id_DATA_WIDTH_A] = 36; // force PDP mode
+ ci->params.erase(id_DATA_WIDTH_W);
rename_bus(ci, "BE", "ADA", 4, 0, 0);
rename_bus(ci, "ADW", "ADA", 9, 0, 5);
rename_bus(ci, "ADR", "ADB", 14, 0, 0);
@@ -1462,23 +1446,23 @@ class Ecp5Packer
rename_bus(ci, "DI", "DIB", 18, 18, 0);
rename_bus(ci, "DO", "DOA", 18, 18, 0);
rename_bus(ci, "DO", "DOB", 18, 0, 0);
- rename_port(ctx, ci, ctx->id("CLKW"), ctx->id("CLKA"));
- rename_port(ctx, ci, ctx->id("CLKR"), ctx->id("CLKB"));
- rename_port(ctx, ci, ctx->id("CEW"), ctx->id("CEA"));
- rename_port(ctx, ci, ctx->id("CER"), ctx->id("CEB"));
- rename_port(ctx, ci, ctx->id("OCER"), ctx->id("OCEB"));
+ rename_port(ctx, ci, id_CLKW, id_CLKA);
+ rename_port(ctx, ci, id_CLKR, id_CLKB);
+ rename_port(ctx, ci, id_CEW, id_CEA);
+ rename_port(ctx, ci, id_CER, id_CEB);
+ rename_port(ctx, ci, id_OCER, id_OCEB);
rename_param(ci, "CLKWMUX", "CLKAMUX");
- if (str_or_default(ci->params, ctx->id("CLKAMUX")) == "CLKW")
- ci->params[ctx->id("CLKAMUX")] = std::string("CLKA");
- if (str_or_default(ci->params, ctx->id("CLKBMUX")) == "CLKR")
- ci->params[ctx->id("CLKBMUX")] = std::string("CLKB");
+ if (str_or_default(ci->params, id_CLKAMUX) == "CLKW")
+ ci->params[id_CLKAMUX] = std::string("CLKA");
+ if (str_or_default(ci->params, id_CLKBMUX) == "CLKR")
+ ci->params[id_CLKBMUX] = std::string("CLKB");
rename_param(ci, "CLKRMUX", "CLKRMUX");
rename_param(ci, "CSDECODE_W", "CSDECODE_A");
rename_param(ci, "CSDECODE_R", "CSDECODE_B");
- std::string outreg = str_or_default(ci->params, ctx->id("REGMODE"), "NOREG");
- ci->params[ctx->id("REGMODE_A")] = outreg;
- ci->params[ctx->id("REGMODE_B")] = outreg;
- ci->params.erase(ctx->id("REGMODE"));
+ std::string outreg = str_or_default(ci->params, id_REGMODE, "NOREG");
+ ci->params[id_REGMODE_A] = outreg;
+ ci->params[id_REGMODE_B] = outreg;
+ ci->params.erase(id_REGMODE);
rename_param(ci, "DATA_WIDTH_R", "DATA_WIDTH_B");
if (ci->ports.count(id_RST)) {
autocreate_empty_port(ci, id_RSTA);
@@ -1525,7 +1509,7 @@ class Ecp5Packer
autocreate_empty_port(ci, id_WEB);
autocreate_empty_port(ci, id_RSTB);
- ci->attrs[ctx->id("WID")] = wid++;
+ ci->attrs[id_WID] = wid++;
}
}
}
@@ -1615,9 +1599,9 @@ class Ecp5Packer
// Placement doesn't work if only one or the other of
// the ALU and MULTs have a BEL specified.
- auto alu_has_bel = alu->attrs.count(ctx->id("BEL"));
+ auto alu_has_bel = alu->attrs.count(id_BEL);
for (auto mult : {mult_a, mult_b}) {
- auto mult_has_bel = mult->attrs.count(ctx->id("BEL"));
+ auto mult_has_bel = mult->attrs.count(id_BEL);
if (alu_has_bel && !mult_has_bel) {
log_error("ALU54B '%s' has a fixed BEL specified, but connected "
"MULT18X18D '%s' does not, specify both or neither.\n",
@@ -1632,8 +1616,8 @@ class Ecp5Packer
// Cannot have MULT OUTPUT_CLK set when connected to an ALU unless
// MULT_BYPASS is also enabled.
for (auto mult : {mult_a, mult_b}) {
- if (str_or_default(mult->params, ctx->id("REG_OUTPUT_CLK"), "NONE") != "NONE" &&
- str_or_default(mult->params, ctx->id("MULT_BYPASS"), "DISABLED") != "ENABLED") {
+ if (str_or_default(mult->params, id_REG_OUTPUT_CLK, "NONE") != "NONE" &&
+ str_or_default(mult->params, id_MULT_BYPASS, "DISABLED") != "ENABLED") {
log_error("MULT18X18D '%s' REG_OUTPUT_CLK must be NONE when driving ALU without MULT_BYPASS\n",
mult->name.c_str(ctx));
}
@@ -1700,27 +1684,27 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (ci->type == id_DCUA) {
- if (ci->attrs.count(ctx->id("LOC"))) {
- std::string loc = ci->attrs.at(ctx->id("LOC")).as_string();
+ if (ci->attrs.count(id_LOC)) {
+ std::string loc = ci->attrs.at(id_LOC).as_string();
if (loc == "DCU0" &&
(ctx->args.type == ArchArgs::LFE5UM_25F || ctx->args.type == ArchArgs::LFE5UM5G_25F))
- ci->attrs[ctx->id("BEL")] = std::string("X42/Y50/DCU");
+ ci->attrs[id_BEL] = std::string("X42/Y50/DCU");
else if (loc == "DCU0" &&
(ctx->args.type == ArchArgs::LFE5UM_45F || ctx->args.type == ArchArgs::LFE5UM5G_45F))
- ci->attrs[ctx->id("BEL")] = std::string("X42/Y71/DCU");
+ ci->attrs[id_BEL] = std::string("X42/Y71/DCU");
else if (loc == "DCU1" &&
(ctx->args.type == ArchArgs::LFE5UM_45F || ctx->args.type == ArchArgs::LFE5UM5G_45F))
- ci->attrs[ctx->id("BEL")] = std::string("X69/Y71/DCU");
+ ci->attrs[id_BEL] = std::string("X69/Y71/DCU");
else if (loc == "DCU0" &&
(ctx->args.type == ArchArgs::LFE5UM_85F || ctx->args.type == ArchArgs::LFE5UM5G_85F))
- ci->attrs[ctx->id("BEL")] = std::string("X46/Y95/DCU");
+ ci->attrs[id_BEL] = std::string("X46/Y95/DCU");
else if (loc == "DCU1" &&
(ctx->args.type == ArchArgs::LFE5UM_85F || ctx->args.type == ArchArgs::LFE5UM5G_85F))
- ci->attrs[ctx->id("BEL")] = std::string("X71/Y95/DCU");
+ ci->attrs[id_BEL] = std::string("X71/Y95/DCU");
else
log_error("no DCU location '%s' in device '%s'\n", loc.c_str(), ctx->getChipName().c_str());
}
- if (!ci->attrs.count(ctx->id("BEL")))
+ if (!ci->attrs.count(id_BEL))
log_error("DCU must be constrained to a Bel!\n");
// Empty port auto-creation to generate correct tie-downs
BelId exemplar_bel;
@@ -1741,7 +1725,7 @@ class Ecp5Packer
if (net == nullptr || net->driver.cell == nullptr)
continue;
IdString ct = net->driver.cell->type;
- if (ct == ctx->id("GND") || ct == ctx->id("VCC")) {
+ if (ct == id_GND || ct == id_VCC) {
disconnect_port(ctx, ci, ndport);
ci->ports.erase(ndport);
}
@@ -1755,8 +1739,8 @@ class Ecp5Packer
CellInfo *dcu = nullptr;
std::string loc_bel = std::string("NONE");
std::string dcu_bel = std::string("NONE");
- if (ci->attrs.count(ctx->id("LOC"))) {
- std::string loc = ci->attrs.at(ctx->id("LOC")).as_string();
+ if (ci->attrs.count(id_LOC)) {
+ std::string loc = ci->attrs.at(id_LOC).as_string();
if (loc == "EXTREF0" &&
(ctx->args.type == ArchArgs::LFE5UM_25F || ctx->args.type == ArchArgs::LFE5UM5G_25F))
loc_bel = std::string("X42/Y50/EXTREF");
@@ -1783,9 +1767,9 @@ class Ecp5Packer
dcu = user.cell;
}
if (dcu != nullptr) {
- if (!dcu->attrs.count(ctx->id("BEL")))
+ if (!dcu->attrs.count(id_BEL))
log_error("DCU must be constrained to a Bel!\n");
- dcu_bel = dcu->attrs.at(ctx->id("BEL")).as_string();
+ dcu_bel = dcu->attrs.at(id_BEL).as_string();
NPNR_ASSERT(dcu_bel.substr(dcu_bel.length() - 3) == "DCU");
dcu_bel.replace(dcu_bel.length() - 3, 3, "EXTREF");
}
@@ -1793,10 +1777,10 @@ class Ecp5Packer
if (dcu_bel == "NONE" && loc_bel == "NONE") {
log_error("EXTREFB has neither a LOC or a directly associated DCUA\n");
} else if (dcu_bel == "NONE") {
- ci->attrs[ctx->id("BEL")] = loc_bel;
+ ci->attrs[id_BEL] = loc_bel;
dcu_bel = loc_bel;
} else if (loc_bel == "NONE") {
- ci->attrs[ctx->id("BEL")] = dcu_bel;
+ ci->attrs[id_BEL] = dcu_bel;
} else {
log_error("EXTREFB has conflicting LOC '%s' and associated DCUA '%s'\n", loc_bel.c_str(),
dcu_bel.c_str());
@@ -1804,17 +1788,17 @@ class Ecp5Packer
} else {
if (dcu_bel == "NONE")
log_error("EXTREFB has no LOC or associated DCUA\n");
- ci->attrs[ctx->id("BEL")] = dcu_bel;
+ ci->attrs[id_BEL] = dcu_bel;
}
} else if (ci->type == id_PCSCLKDIV) {
const NetInfo *clki = net_or_nullptr(ci, id_CLKI);
if (clki != nullptr && clki->driver.cell != nullptr && clki->driver.cell->type == id_DCUA) {
CellInfo *dcu = clki->driver.cell;
- if (!dcu->attrs.count(ctx->id("BEL")))
+ if (!dcu->attrs.count(id_BEL))
log_error("DCU must be constrained to a Bel!\n");
- BelId bel = ctx->getBelByNameStr(dcu->attrs.at(ctx->id("BEL")).as_string());
+ BelId bel = ctx->getBelByNameStr(dcu->attrs.at(id_BEL).as_string());
if (bel == BelId())
- log_error("Invalid DCU bel '%s'\n", dcu->attrs.at(ctx->id("BEL")).c_str());
+ log_error("Invalid DCU bel '%s'\n", dcu->attrs.at(id_BEL).c_str());
Loc loc = ctx->getBelLocation(bel);
// DCU0 -> CLKDIV z=0; DCU1 -> CLKDIV z=1
ci->constr_abs_z = true;
@@ -1830,18 +1814,17 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (ci->type == id_USRMCLK) {
- rename_port(ctx, ci, ctx->id("USRMCLKI"), id_PADDO);
- rename_port(ctx, ci, ctx->id("USRMCLKTS"), id_PADDT);
- rename_port(ctx, ci, ctx->id("USRMCLKO"), id_PADDI);
- } else if (ci->type == id_GSR || ci->type == ctx->id("SGSR")) {
- ci->params[ctx->id("MODE")] = std::string("ACTIVE_LOW");
- ci->params[ctx->id("SYNCMODE")] =
- ci->type == ctx->id("SGSR") ? std::string("SYNC") : std::string("ASYNC");
+ rename_port(ctx, ci, id_USRMCLKI, id_PADDO);
+ rename_port(ctx, ci, id_USRMCLKTS, id_PADDT);
+ rename_port(ctx, ci, id_USRMCLKO, id_PADDI);
+ } else if (ci->type == id_GSR || ci->type == id_SGSR) {
+ ci->params[id_MODE] = std::string("ACTIVE_LOW");
+ ci->params[id_SYNCMODE] = ci->type == id_SGSR ? std::string("SYNC") : std::string("ASYNC");
ci->type = id_GSR;
for (BelId bel : ctx->getBels()) {
if (ctx->getBelType(bel) != id_GSR)
continue;
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
ctx->gsrclk_wire = ctx->getBelPinWire(bel, id_CLK);
}
}
@@ -1858,20 +1841,20 @@ class Ecp5Packer
}
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
- if (ci->type == id_EHXPLLL && ci->attrs.count(ctx->id("BEL")))
- available_plls.erase(ctx->getBelByNameStr(ci->attrs.at(ctx->id("BEL")).as_string()));
+ if (ci->type == id_EHXPLLL && ci->attrs.count(id_BEL))
+ available_plls.erase(ctx->getBelByNameStr(ci->attrs.at(id_BEL).as_string()));
}
// Place PLL connected to fixed drivers such as IO close to their source
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
- if (ci->type == id_EHXPLLL && !ci->attrs.count(ctx->id("BEL"))) {
+ if (ci->type == id_EHXPLLL && !ci->attrs.count(id_BEL)) {
const NetInfo *drivernet = net_or_nullptr(ci, id_CLKI);
if (drivernet == nullptr || drivernet->driver.cell == nullptr)
continue;
const CellInfo *drivercell = drivernet->driver.cell;
- if (!drivercell->attrs.count(ctx->id("BEL")))
+ if (!drivercell->attrs.count(id_BEL))
continue;
- BelId drvbel = ctx->getBelByNameStr(drivercell->attrs.at(ctx->id("BEL")).as_string());
+ BelId drvbel = ctx->getBelByNameStr(drivercell->attrs.at(id_BEL).as_string());
Loc drvloc = ctx->getBelLocation(drvbel);
BelId closest_pll;
int closest_distance = std::numeric_limits<int>::max();
@@ -1886,18 +1869,18 @@ class Ecp5Packer
if (closest_pll == BelId())
log_error("failed to place PLL '%s'\n", ci->name.c_str(ctx));
available_plls.erase(closest_pll);
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(closest_pll).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(closest_pll).str(ctx);
}
}
// Place PLLs driven by logic, etc, randomly
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
- if (ci->type == id_EHXPLLL && !ci->attrs.count(ctx->id("BEL"))) {
+ if (ci->type == id_EHXPLLL && !ci->attrs.count(id_BEL)) {
if (available_plls.empty())
log_error("failed to place PLL '%s'\n", ci->name.c_str(ctx));
BelId next_pll = *(available_plls.begin());
available_plls.erase(next_pll);
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(next_pll).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(next_pll).str(ctx);
}
}
}
@@ -1907,7 +1890,7 @@ class Ecp5Packer
{
if (a->driver.cell == nullptr || b->driver.cell == nullptr)
return (a->driver.cell == nullptr && b->driver.cell == nullptr);
- if (a->driver.cell->type != ctx->id("GND") && a->driver.cell->type != ctx->id("VCC"))
+ if (a->driver.cell->type != id_GND && a->driver.cell->type != id_VCC)
return false;
return a->driver.cell->type == b->driver.cell->type;
}
@@ -1955,7 +1938,7 @@ class Ecp5Packer
std::to_string(free_eclk));
NetInfo *promoted_ecknet = ctx->createNet(eckname);
- promoted_ecknet->attrs[ctx->id("ECP5_IS_GLOBAL")] = 1; // Prevents router etc touching this special net
+ promoted_ecknet->attrs[id_ECP5_IS_GLOBAL] = 1; // Prevents router etc touching this special net
eclk.buf = promoted_ecknet;
// Insert TRELLIS_ECLKBUF to isolate edge clock from general routing
@@ -1974,7 +1957,7 @@ class Ecp5Packer
}
NPNR_ASSERT(target_bel != BelId());
- eclkbuf->attrs[ctx->id("BEL")] = ctx->getBelName(target_bel).str(ctx);
+ eclkbuf->attrs[id_BEL] = ctx->getBelName(target_bel).str(ctx);
connect_port(ctx, ecknet, eclkbuf.get(), id_ECLKI);
connect_port(ctx, eclk.buf, eclkbuf.get(), id_ECLKO);
@@ -2038,10 +2021,10 @@ class Ecp5Packer
}
IdString name = ctx->id(ci->name.str(ctx) + "$zero$" + port.str(ctx));
- auto zero_cell = std::make_unique<CellInfo>(ctx, name, ctx->id("GND"));
+ auto zero_cell = std::make_unique<CellInfo>(ctx, name, id_GND);
NetInfo *zero_net = ctx->createNet(name);
- zero_cell->addOutput(ctx->id("GND"));
- connect_port(ctx, zero_net, zero_cell.get(), ctx->id("GND"));
+ zero_cell->addOutput(id_GND);
+ connect_port(ctx, zero_net, zero_cell.get(), id_GND);
connect_port(ctx, zero_net, ci, port);
new_cells.push_back(std::move(zero_cell));
}
@@ -2053,15 +2036,15 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (ci->type == id_DQSBUFM) {
- CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("DQSI")).net, is_trellis_io, id_O);
- if (pio == nullptr || ci->ports.at(ctx->id("DQSI")).net->users.size() > 1)
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_DQSI).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(id_DQSI).net->users.size() > 1)
log_error("DQSBUFM '%s' DQSI input must be connected only to a top level input\n",
ci->name.c_str(ctx));
- if (!pio->attrs.count(ctx->id("BEL")))
+ if (!pio->attrs.count(id_BEL))
log_error("DQSBUFM can only be used with a pin-constrained PIO connected to its DQSI input"
"(while processing '%s').\n",
ci->name.c_str(ctx));
- BelId pio_bel = ctx->getBelByNameStr(pio->attrs.at(ctx->id("BEL")).as_string());
+ BelId pio_bel = ctx->getBelByNameStr(pio->attrs.at(id_BEL).as_string());
NPNR_ASSERT(pio_bel != BelId());
Loc pio_loc = ctx->getBelLocation(pio_bel);
if (pio_loc.z != 0)
@@ -2072,7 +2055,7 @@ class Ecp5Packer
if (dqsbuf == BelId() || ctx->getBelType(dqsbuf) != id_DQSBUFM)
log_error("PIO '%s' does not appear to be a DQS site (didn't find a DQSBUFM).\n",
ctx->nameOfBel(pio_bel));
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(dqsbuf).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(dqsbuf).str(ctx);
bool got_dqsg =
ctx->get_pio_dqs_group(pio_bel, dqsbuf_dqsg[ci->name].first, dqsbuf_dqsg[ci->name].second);
NPNR_ASSERT(got_dqsg);
@@ -2088,15 +2071,14 @@ class Ecp5Packer
if (pn == nullptr)
continue;
for (auto &usr : pn->users) {
- if (usr.port != port ||
- (usr.cell->type != ctx->id("ODDRX2DQA") && usr.cell->type != ctx->id("ODDRX2DQSB") &&
- usr.cell->type != ctx->id("TSHX2DQSA") && usr.cell->type != ctx->id("IDDRX2DQA") &&
- usr.cell->type != ctx->id("TSHX2DQA") && usr.cell->type != id_IOLOGIC))
+ if (usr.port != port || (usr.cell->type != id_ODDRX2DQA && usr.cell->type != id_ODDRX2DQSB &&
+ usr.cell->type != id_TSHX2DQSA && usr.cell->type != id_IDDRX2DQA &&
+ usr.cell->type != id_TSHX2DQA && usr.cell->type != id_IOLOGIC))
log_error("Port '%s' of DQSBUFM '%s' cannot drive port '%s' of cell '%s'.\n",
port.c_str(ctx), ci->name.c_str(ctx), usr.port.c_str(ctx),
usr.cell->name.c_str(ctx));
}
- pn->attrs[ctx->id("ECP5_IS_GLOBAL")] = 1;
+ pn->attrs[id_ECP5_IS_GLOBAL] = 1;
}
for (auto zport :
@@ -2146,9 +2128,9 @@ class Ecp5Packer
if (prim->ports.count(port))
sclk = prim->ports[port].net;
if (sclk == nullptr) {
- iol->params[input ? ctx->id("CLKIMUX") : ctx->id("CLKOMUX")] = std::string("0");
+ iol->params[input ? id_CLKIMUX : id_CLKOMUX] = std::string("0");
} else {
- iol->params[input ? ctx->id("CLKIMUX") : ctx->id("CLKOMUX")] = std::string("CLK");
+ iol->params[input ? id_CLKIMUX : id_CLKOMUX] = std::string("CLK");
if (iol->ports[id_CLK].net != nullptr) {
if (iol->ports[id_CLK].net != sclk && !equal_constant(iol->ports[id_CLK].net, sclk))
log_error("IOLOGIC '%s' has conflicting clocks '%s' and '%s'\n", iol->name.c_str(ctx),
@@ -2184,9 +2166,9 @@ class Ecp5Packer
if (prim->ports.count(port))
lsr = prim->ports[port].net;
if (lsr == nullptr) {
- iol->params[input ? ctx->id("LSRIMUX") : ctx->id("LSROMUX")] = std::string("0");
+ iol->params[input ? id_LSRIMUX : id_LSROMUX] = std::string("0");
} else {
- iol->params[input ? ctx->id("LSRIMUX") : ctx->id("LSROMUX")] = std::string("LSRMUX");
+ iol->params[input ? id_LSRIMUX : id_LSROMUX] = std::string("LSRMUX");
if (iol->ports[id_LSR].net != nullptr && !equal_constant(iol->ports[id_LSR].net, lsr)) {
if (iol->ports[id_LSR].net != lsr)
log_error("IOLOGIC '%s' has conflicting LSR signals '%s' and '%s'\n", iol->name.c_str(ctx),
@@ -2202,7 +2184,7 @@ class Ecp5Packer
bool warned_oddrx_iddrx = false;
auto set_iologic_mode = [&](CellInfo *iol, std::string mode) {
- auto &curr_mode = iol->params[ctx->id("MODE")].str;
+ auto &curr_mode = iol->params[id_MODE].str;
if (curr_mode != "NONE" && mode == "IREG_OREG")
return;
if ((curr_mode == "IDDRXN" && mode == "ODDRXN") || (curr_mode == "ODDRXN" && mode == "IDDRXN")) {
@@ -2223,11 +2205,11 @@ class Ecp5Packer
};
auto get_pio_bel = [&](CellInfo *pio, CellInfo *curr) {
- if (!pio->attrs.count(ctx->id("BEL")))
+ if (!pio->attrs.count(id_BEL))
log_error("IOLOGIC functionality (DDR, DELAY, DQS, etc) can only be used with pin-constrained PIO "
"(while processing '%s').\n",
curr->name.c_str(ctx));
- BelId bel = ctx->getBelByNameStr(pio->attrs.at(ctx->id("BEL")).as_string());
+ BelId bel = ctx->getBelByNameStr(pio->attrs.at(id_BEL).as_string());
NPNR_ASSERT(bel != BelId());
return bel;
};
@@ -2243,7 +2225,7 @@ class Ecp5Packer
create_ecp5_cell(ctx, s ? id_SIOLOGIC : id_IOLOGIC, pio->name.str(ctx) + "$IOL");
loc.z += s ? 2 : 4;
- iol->attrs[ctx->id("BEL")] = ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx);
+ iol->attrs[id_BEL] = ctx->getBelName(ctx->getBelByLocation(loc)).str(ctx);
CellInfo *iol_ptr = iol.get();
pio_iologic[pio->name] = iol_ptr;
@@ -2287,22 +2269,21 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
- if (ci->type == ctx->id("DELAYF") || ci->type == ctx->id("DELAYG")) {
- CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(ctx->id("A")).net, is_trellis_io, id_O);
- CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(ctx->id("Z")).net, is_trellis_io, id_I, true);
+ if (ci->type == id_DELAYF || ci->type == id_DELAYG) {
+ CellInfo *i_pio = net_driven_by(ctx, ci->ports.at(id_A).net, is_trellis_io, id_O);
+ CellInfo *o_pio = net_only_drives(ctx, ci->ports.at(id_Z).net, is_trellis_io, id_I, true);
CellInfo *iol = nullptr;
- if (i_pio != nullptr && ci->ports.at(ctx->id("A")).net->users.size() == 1) {
+ if (i_pio != nullptr && ci->ports.at(id_A).net->users.size() == 1) {
iol = create_pio_iologic(i_pio, ci);
set_iologic_mode(iol, "IREG_OREG");
bool drives_iologic = false;
- for (auto user : ci->ports.at(ctx->id("Z")).net->users)
+ for (auto user : ci->ports.at(id_Z).net->users)
if (is_iologic_input_cell(ctx, user.cell) &&
- (user.port == ctx->id("D") ||
- (user.cell->type == ctx->id("TRELLIS_FF") && user.port == ctx->id("DI"))))
+ (user.port == id_D || (user.cell->type == id_TRELLIS_FF && user.port == id_DI)))
drives_iologic = true;
if (drives_iologic) {
// Reconnect to PIO which the packer expects later on
- NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
+ NetInfo *input_net = ci->ports.at(id_A).net, *dly_net = ci->ports.at(id_Z).net;
disconnect_port(ctx, i_pio, id_O);
i_pio->ports.at(id_O).net = nullptr;
disconnect_port(ctx, ci, id_A);
@@ -2321,9 +2302,9 @@ class Ecp5Packer
iol = create_pio_iologic(o_pio, ci);
iol->params[ctx->id("DELAY.OUTDEL")] = std::string("ENABLED");
bool driven_by_iol = false;
- NetInfo *input_net = ci->ports.at(ctx->id("A")).net, *dly_net = ci->ports.at(ctx->id("Z")).net;
+ NetInfo *input_net = ci->ports.at(id_A).net, *dly_net = ci->ports.at(id_Z).net;
if (input_net->driver.cell != nullptr && is_iologic_output_cell(ctx, input_net->driver.cell) &&
- input_net->driver.port == ctx->id("Q"))
+ input_net->driver.port == id_Q)
driven_by_iol = true;
if (driven_by_iol) {
disconnect_port(ctx, o_pio, id_I);
@@ -2335,8 +2316,8 @@ class Ecp5Packer
connect_port(ctx, input_net, o_pio, id_I);
ctx->nets.erase(dly_net->name);
} else {
- replace_port(ci, ctx->id("A"), iol, id_TXDATA0);
- replace_port(ci, ctx->id("Z"), iol, id_IOLDO);
+ replace_port(ci, id_A, iol, id_TXDATA0);
+ replace_port(ci, id_Z, iol, id_IOLDO);
if (!o_pio->ports.count(id_IOLDO)) {
o_pio->ports[id_IOLDO].name = id_IOLDO;
o_pio->ports[id_IOLDO].type = PORT_IN;
@@ -2349,11 +2330,11 @@ class Ecp5Packer
ci->name.c_str(ctx));
}
iol->params[ctx->id("DELAY.DEL_VALUE")] =
- lookup_delay(str_or_default(ci->params, ctx->id("DEL_MODE"), "USER_DEFINED"));
- if (ci->params.count(ctx->id("DEL_VALUE")) &&
- (!ci->params.at(ctx->id("DEL_VALUE")).is_string ||
- std::string(ci->params.at(ctx->id("DEL_VALUE")).as_string()).substr(0, 5) != "DELAY"))
- iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(ctx->id("DEL_VALUE"));
+ lookup_delay(str_or_default(ci->params, id_DEL_MODE, "USER_DEFINED"));
+ if (ci->params.count(id_DEL_VALUE) &&
+ (!ci->params.at(id_DEL_VALUE).is_string ||
+ std::string(ci->params.at(id_DEL_VALUE).as_string()).substr(0, 5) != "DELAY"))
+ iol->params[ctx->id("DELAY.DEL_VALUE")] = ci->params.at(id_DEL_VALUE);
if (ci->ports.count(id_LOADN))
replace_port(ci, id_LOADN, iol, id_LOADN);
else
@@ -2373,9 +2354,9 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
- if (ci->type == ctx->id("IDDRX1F")) {
- CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
- if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+ if (ci->type == id_IDDRX1F) {
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(id_D).net->users.size() > 1)
log_error("IDDRX1F '%s' D input must be connected only to a top level input\n",
ci->name.c_str(ctx));
CellInfo *iol;
@@ -2384,15 +2365,15 @@ class Ecp5Packer
else
iol = create_pio_iologic(pio, ci);
set_iologic_mode(iol, "IDDRX1_ODDRX1");
- replace_port(ci, ctx->id("D"), iol, id_PADDI);
- set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
- set_iologic_lsr(iol, ci, ctx->id("RST"), true);
- replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
- replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
- iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ replace_port(ci, id_D, iol, id_PADDI);
+ set_iologic_sclk(iol, ci, id_SCLK, true);
+ set_iologic_lsr(iol, ci, id_RST, true);
+ replace_port(ci, id_Q0, iol, id_RXDATA0);
+ replace_port(ci, id_Q1, iol, id_RXDATA1);
+ iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
packed_cells.insert(cell.first);
- } else if (ci->type == ctx->id("ODDRX1F")) {
- CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ } else if (ci->type == id_ODDRX1F) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
if (pio == nullptr)
log_error("ODDRX1F '%s' Q output must be connected only to a top level output\n",
ci->name.c_str(ctx));
@@ -2402,21 +2383,21 @@ class Ecp5Packer
else
iol = create_pio_iologic(pio, ci);
set_iologic_mode(iol, "IDDRX1_ODDRX1");
- replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ replace_port(ci, id_Q, iol, id_IOLDO);
if (!pio->ports.count(id_IOLDO)) {
pio->ports[id_IOLDO].name = id_IOLDO;
pio->ports[id_IOLDO].type = PORT_IN;
}
replace_port(pio, id_I, pio, id_IOLDO);
- pio->params[ctx->id("DATAMUX_ODDR")] = std::string("IOLDO");
- set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
- set_iologic_lsr(iol, ci, ctx->id("RST"), false);
- replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
- replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
- iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ pio->params[id_DATAMUX_ODDR] = std::string("IOLDO");
+ set_iologic_sclk(iol, ci, id_SCLK, false);
+ set_iologic_lsr(iol, ci, id_RST, false);
+ replace_port(ci, id_D0, iol, id_TXDATA0);
+ replace_port(ci, id_D1, iol, id_TXDATA1);
+ iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
packed_cells.insert(cell.first);
- } else if (ci->type == ctx->id("ODDRX2F") || ci->type == ctx->id("ODDR71B")) {
- CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ } else if (ci->type == id_ODDRX2F || ci->type == id_ODDR71B) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
if (pio == nullptr)
log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
ci->name.c_str(ctx));
@@ -2426,38 +2407,38 @@ class Ecp5Packer
else
iol = create_pio_iologic(pio, ci);
set_iologic_mode(iol, "ODDRXN");
- replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ replace_port(ci, id_Q, iol, id_IOLDO);
if (!pio->ports.count(id_IOLDO)) {
pio->ports[id_IOLDO].name = id_IOLDO;
pio->ports[id_IOLDO].type = PORT_IN;
}
replace_port(pio, id_I, pio, id_IOLDO);
- set_iologic_sclk(iol, ci, ctx->id("SCLK"), false, false);
- set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+ set_iologic_sclk(iol, ci, id_SCLK, false, false);
+ set_iologic_sclk(iol, ci, id_SCLK, true);
set_iologic_eclk(iol, ci, id_ECLK);
- set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
- set_iologic_lsr(iol, ci, ctx->id("RST"), true);
- replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
- replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
- replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
- replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
- if (ci->type == ctx->id("ODDR71B")) {
- Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(pio->attrs.at(ctx->id("BEL")).as_string()));
+ set_iologic_lsr(iol, ci, id_RST, false, false);
+ set_iologic_lsr(iol, ci, id_RST, true);
+ replace_port(ci, id_D0, iol, id_TXDATA0);
+ replace_port(ci, id_D1, iol, id_TXDATA1);
+ replace_port(ci, id_D2, iol, id_TXDATA2);
+ replace_port(ci, id_D3, iol, id_TXDATA3);
+ if (ci->type == id_ODDR71B) {
+ Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(pio->attrs.at(id_BEL).as_string()));
if (loc.z % 2 == 1)
log_error("ODDR71B '%s' can only be used at 'A' or 'C' locations\n", ci->name.c_str(ctx));
- replace_port(ci, ctx->id("D4"), iol, id_TXDATA4);
- replace_port(ci, ctx->id("D5"), iol, id_TXDATA5);
- replace_port(ci, ctx->id("D6"), iol, id_TXDATA6);
+ replace_port(ci, id_D4, iol, id_TXDATA4);
+ replace_port(ci, id_D5, iol, id_TXDATA5);
+ replace_port(ci, id_D6, iol, id_TXDATA6);
iol->params[ctx->id("ODDRXN.MODE")] = std::string("ODDR71");
} else {
iol->params[ctx->id("ODDRXN.MODE")] = std::string("ODDRX2");
}
- iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
- pio->params[ctx->id("DATAMUX_ODDR")] = std::string("IOLDO");
+ iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
+ pio->params[id_DATAMUX_ODDR] = std::string("IOLDO");
packed_cells.insert(cell.first);
- } else if (ci->type == ctx->id("IDDRX2F") || ci->type == ctx->id("IDDR71B")) {
- CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
- if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+ } else if (ci->type == id_IDDRX2F || ci->type == id_IDDR71B) {
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(id_D).net->users.size() > 1)
log_error("%s '%s' D input must be connected only to a top level input\n", ci->type.c_str(ctx),
ci->name.c_str(ctx));
CellInfo *iol;
@@ -2466,30 +2447,30 @@ class Ecp5Packer
else
iol = create_pio_iologic(pio, ci);
set_iologic_mode(iol, "IDDRXN");
- replace_port(ci, ctx->id("D"), iol, id_PADDI);
- set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+ replace_port(ci, id_D, iol, id_PADDI);
+ set_iologic_sclk(iol, ci, id_SCLK, true);
set_iologic_eclk(iol, ci, id_ECLK);
- set_iologic_lsr(iol, ci, ctx->id("RST"), true);
- replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
- replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
- replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
- replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
- if (ci->type == ctx->id("IDDR71B")) {
- Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(pio->attrs.at(ctx->id("BEL")).as_string()));
+ set_iologic_lsr(iol, ci, id_RST, true);
+ replace_port(ci, id_Q0, iol, id_RXDATA0);
+ replace_port(ci, id_Q1, iol, id_RXDATA1);
+ replace_port(ci, id_Q2, iol, id_RXDATA2);
+ replace_port(ci, id_Q3, iol, id_RXDATA3);
+ if (ci->type == id_IDDR71B) {
+ Loc loc = ctx->getBelLocation(ctx->getBelByNameStr(pio->attrs.at(id_BEL).as_string()));
if (loc.z % 2 == 1)
log_error("IDDR71B '%s' can only be used at 'A' or 'C' locations\n", ci->name.c_str(ctx));
- replace_port(ci, ctx->id("Q4"), iol, id_RXDATA4);
- replace_port(ci, ctx->id("Q5"), iol, id_RXDATA5);
- replace_port(ci, ctx->id("Q6"), iol, id_RXDATA6);
- replace_port(ci, ctx->id("ALIGNWD"), iol, id_SLIP);
+ replace_port(ci, id_Q4, iol, id_RXDATA4);
+ replace_port(ci, id_Q5, iol, id_RXDATA5);
+ replace_port(ci, id_Q6, iol, id_RXDATA6);
+ replace_port(ci, id_ALIGNWD, iol, id_SLIP);
iol->params[ctx->id("IDDRXN.MODE")] = std::string("IDDR71");
} else {
iol->params[ctx->id("IDDRXN.MODE")] = std::string("IDDRX2");
}
- iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
packed_cells.insert(cell.first);
- } else if (ci->type == ctx->id("OSHX2A")) {
- CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ } else if (ci->type == id_OSHX2A) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
if (pio == nullptr)
log_error("OSHX2A '%s' Q output must be connected only to a top level output\n",
ci->name.c_str(ctx));
@@ -2499,24 +2480,24 @@ class Ecp5Packer
else
iol = create_pio_iologic(pio, ci);
set_iologic_mode(iol, "MIDDRX_MODDRX");
- replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ replace_port(ci, id_Q, iol, id_IOLDO);
if (!pio->ports.count(id_IOLDO)) {
pio->ports[id_IOLDO].name = id_IOLDO;
pio->ports[id_IOLDO].type = PORT_IN;
}
replace_port(pio, id_I, pio, id_IOLDO);
- set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_sclk(iol, ci, id_SCLK, false);
set_iologic_eclk(iol, ci, id_ECLK);
- set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
- set_iologic_lsr(iol, ci, ctx->id("RST"), true);
- replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
- replace_port(ci, ctx->id("D1"), iol, id_TXDATA2);
- iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ set_iologic_lsr(iol, ci, id_RST, false, false);
+ set_iologic_lsr(iol, ci, id_RST, true);
+ replace_port(ci, id_D0, iol, id_TXDATA0);
+ replace_port(ci, id_D1, iol, id_TXDATA2);
+ iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
iol->params[ctx->id("MODDRX.MODE")] = std::string("MOSHX2");
- pio->params[ctx->id("DATAMUX_MDDR")] = std::string("IOLDO");
+ pio->params[id_DATAMUX_MDDR] = std::string("IOLDO");
packed_cells.insert(cell.first);
- } else if (ci->type == ctx->id("ODDRX2DQA") || ci->type == ctx->id("ODDRX2DQSB")) {
- CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ } else if (ci->type == id_ODDRX2DQA || ci->type == id_ODDRX2DQSB) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
if (pio == nullptr)
log_error("%s '%s' Q output must be connected only to a top level output\n", ci->type.c_str(ctx),
ci->name.c_str(ctx));
@@ -2526,30 +2507,30 @@ class Ecp5Packer
else
iol = create_pio_iologic(pio, ci);
set_iologic_mode(iol, "MIDDRX_MODDRX");
- replace_port(ci, ctx->id("Q"), iol, id_IOLDO);
+ replace_port(ci, id_Q, iol, id_IOLDO);
if (!pio->ports.count(id_IOLDO)) {
pio->ports[id_IOLDO].name = id_IOLDO;
pio->ports[id_IOLDO].type = PORT_IN;
}
replace_port(pio, id_I, pio, id_IOLDO);
- set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_sclk(iol, ci, id_SCLK, false);
set_iologic_eclk(iol, ci, id_ECLK);
- set_iologic_lsr(iol, ci, ctx->id("RST"), false, false);
- set_iologic_lsr(iol, ci, ctx->id("RST"), true);
- replace_port(ci, ctx->id("D0"), iol, id_TXDATA0);
- replace_port(ci, ctx->id("D1"), iol, id_TXDATA1);
- replace_port(ci, ctx->id("D2"), iol, id_TXDATA2);
- replace_port(ci, ctx->id("D3"), iol, id_TXDATA3);
- iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ set_iologic_lsr(iol, ci, id_RST, false, false);
+ set_iologic_lsr(iol, ci, id_RST, true);
+ replace_port(ci, id_D0, iol, id_TXDATA0);
+ replace_port(ci, id_D1, iol, id_TXDATA1);
+ replace_port(ci, id_D2, iol, id_TXDATA2);
+ replace_port(ci, id_D3, iol, id_TXDATA3);
+ iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
iol->params[ctx->id("MODDRX.MODE")] = std::string("MODDRX2");
iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] =
- std::string(ci->type == ctx->id("ODDRX2DQSB") ? "DQSW" : "DQSW270");
- process_dqs_port(ci, pio, iol, ci->type == ctx->id("ODDRX2DQSB") ? id_DQSW : id_DQSW270);
- pio->params[ctx->id("DATAMUX_MDDR")] = std::string("IOLDO");
+ std::string(ci->type == id_ODDRX2DQSB ? "DQSW" : "DQSW270");
+ process_dqs_port(ci, pio, iol, ci->type == id_ODDRX2DQSB ? id_DQSW : id_DQSW270);
+ pio->params[id_DATAMUX_MDDR] = std::string("IOLDO");
packed_cells.insert(cell.first);
- } else if (ci->type == ctx->id("IDDRX2DQA")) {
- CellInfo *pio = net_driven_by(ctx, ci->ports.at(ctx->id("D")).net, is_trellis_io, id_O);
- if (pio == nullptr || ci->ports.at(ctx->id("D")).net->users.size() > 1)
+ } else if (ci->type == id_IDDRX2DQA) {
+ CellInfo *pio = net_driven_by(ctx, ci->ports.at(id_D).net, is_trellis_io, id_O);
+ if (pio == nullptr || ci->ports.at(id_D).net->users.size() > 1)
log_error("IDDRX2DQA '%s' D input must be connected only to a top level input\n",
ci->name.c_str(ctx));
CellInfo *iol;
@@ -2558,16 +2539,16 @@ class Ecp5Packer
else
iol = create_pio_iologic(pio, ci);
set_iologic_mode(iol, "MIDDRX_MODDRX");
- replace_port(ci, ctx->id("D"), iol, id_PADDI);
- set_iologic_sclk(iol, ci, ctx->id("SCLK"), true);
+ replace_port(ci, id_D, iol, id_PADDI);
+ set_iologic_sclk(iol, ci, id_SCLK, true);
set_iologic_eclk(iol, ci, id_ECLK);
- set_iologic_lsr(iol, ci, ctx->id("RST"), true);
- replace_port(ci, ctx->id("Q0"), iol, id_RXDATA0);
- replace_port(ci, ctx->id("Q1"), iol, id_RXDATA1);
- replace_port(ci, ctx->id("Q2"), iol, id_RXDATA2);
- replace_port(ci, ctx->id("Q3"), iol, id_RXDATA3);
- replace_port(ci, ctx->id("QWL"), iol, id_INFF);
- iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ set_iologic_lsr(iol, ci, id_RST, true);
+ replace_port(ci, id_Q0, iol, id_RXDATA0);
+ replace_port(ci, id_Q1, iol, id_RXDATA1);
+ replace_port(ci, id_Q2, iol, id_RXDATA2);
+ replace_port(ci, id_Q3, iol, id_RXDATA3);
+ replace_port(ci, id_QWL, iol, id_INFF);
+ iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
iol->params[ctx->id("MIDDRX.MODE")] = std::string("MIDDRX2");
process_dqs_port(ci, pio, iol, id_DQSR90);
process_dqs_port(ci, pio, iol, id_RDPNTR2);
@@ -2577,8 +2558,8 @@ class Ecp5Packer
process_dqs_port(ci, pio, iol, id_WRPNTR1);
process_dqs_port(ci, pio, iol, id_WRPNTR0);
packed_cells.insert(cell.first);
- } else if (ci->type == ctx->id("TSHX2DQA") || ci->type == ctx->id("TSHX2DQSA")) {
- CellInfo *pio = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
+ } else if (ci->type == id_TSHX2DQA || ci->type == id_TSHX2DQSA) {
+ CellInfo *pio = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_T, true);
if (pio == nullptr)
log_error("%s '%s' Q output must be connected only to a top level tristate\n", ci->type.c_str(ctx),
ci->name.c_str(ctx));
@@ -2588,33 +2569,33 @@ class Ecp5Packer
else
iol = create_pio_iologic(pio, ci);
set_iologic_mode(iol, "MIDDRX_MODDRX");
- replace_port(ci, ctx->id("Q"), iol, id_IOLTO);
+ replace_port(ci, id_Q, iol, id_IOLTO);
if (!pio->ports.count(id_IOLTO)) {
pio->ports[id_IOLTO].name = id_IOLTO;
pio->ports[id_IOLTO].type = PORT_IN;
}
replace_port(pio, id_T, pio, id_IOLTO);
- set_iologic_sclk(iol, ci, ctx->id("SCLK"), false);
+ set_iologic_sclk(iol, ci, id_SCLK, false);
set_iologic_eclk(iol, ci, id_ECLK);
- set_iologic_lsr(iol, ci, ctx->id("RST"), false);
- replace_port(ci, ctx->id("T0"), iol, id_TSDATA0);
- replace_port(ci, ctx->id("T1"), iol, id_TSDATA1);
- process_dqs_port(ci, pio, iol, ci->type == ctx->id("TSHX2DQSA") ? id_DQSW : id_DQSW270);
- iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ set_iologic_lsr(iol, ci, id_RST, false);
+ replace_port(ci, id_T0, iol, id_TSDATA0);
+ replace_port(ci, id_T1, iol, id_TSDATA1);
+ process_dqs_port(ci, pio, iol, ci->type == id_TSHX2DQSA ? id_DQSW : id_DQSW270);
+ iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
iol->params[ctx->id("MTDDRX.MODE")] = std::string("MTSHX2");
iol->params[ctx->id("MTDDRX.REGSET")] = std::string("SET");
iol->params[ctx->id("MTDDRX.DQSW_INVERT")] =
- std::string(ci->type == ctx->id("TSHX2DQSA") ? "ENABLED" : "DISABLED");
+ std::string(ci->type == id_TSHX2DQSA ? "ENABLED" : "DISABLED");
iol->params[ctx->id("MIDDRX_MODDRX.WRCLKMUX")] =
- std::string(ci->type == ctx->id("TSHX2DQSA") ? "DQSW" : "DQSW270");
- iol->params[ctx->id("IOLTOMUX")] = std::string("TDDR");
+ std::string(ci->type == id_TSHX2DQSA ? "DQSW" : "DQSW270");
+ iol->params[id_IOLTOMUX] = std::string("TDDR");
packed_cells.insert(cell.first);
- } else if (ci->type == ctx->id("TRELLIS_FF") && bool_or_default(ci->attrs, ctx->id("syn_useioff"))) {
+ } else if (ci->type == id_TRELLIS_FF && bool_or_default(ci->attrs, id_syn_useioff)) {
// Pack IO flipflop into IOLOGIC
- std::string mode = str_or_default(ci->attrs, ctx->id("ioff_dir"), "");
+ std::string mode = str_or_default(ci->attrs, id_ioff_dir, "");
if (mode != "output") {
// See if it can be packed as an input ff
- NetInfo *d = get_net_or_empty(ci, ctx->id("DI"));
+ NetInfo *d = get_net_or_empty(ci, id_DI);
CellInfo *pio = net_driven_by(ctx, d, is_trellis_io, id_O);
if (pio != nullptr && d->users.size() == 1) {
// Input FF
@@ -2624,35 +2605,35 @@ class Ecp5Packer
else
iol = create_pio_iologic(pio, ci);
set_iologic_mode(iol, "IREG_OREG");
- set_iologic_sclk(iol, ci, ctx->id("CLK"), true);
- set_iologic_lsr(iol, ci, ctx->id("LSR"), true);
+ set_iologic_sclk(iol, ci, id_CLK, true);
+ set_iologic_lsr(iol, ci, id_LSR, true);
// Handle CLK and CE muxes
- if (str_or_default(ci->params, ctx->id("CLKMUX")) == "INV")
- iol->params[ctx->id("CLKIMUX")] = std::string("INV");
- if (str_or_default(ci->params, ctx->id("CEMUX"), "CE") == "CE") {
- iol->params[ctx->id("CEIMUX")] = std::string("CEMUX");
- iol->params[ctx->id("CEMUX")] = std::string("CE");
- if (get_net_or_empty(ci, ctx->id("CE")) == nullptr)
- replace_port(ci, ctx->id("CE"), iol, ctx->id("CE"));
+ if (str_or_default(ci->params, id_CLKMUX) == "INV")
+ iol->params[id_CLKIMUX] = std::string("INV");
+ if (str_or_default(ci->params, id_CEMUX, "CE") == "CE") {
+ iol->params[id_CEIMUX] = std::string("CEMUX");
+ iol->params[id_CEMUX] = std::string("CE");
+ if (get_net_or_empty(ci, id_CE) == nullptr)
+ replace_port(ci, id_CE, iol, id_CE);
else
- disconnect_port(ctx, ci, ctx->id("CE"));
+ disconnect_port(ctx, ci, id_CE);
} else {
- iol->params[ctx->id("CEIMUX")] = std::string("1");
+ iol->params[id_CEIMUX] = std::string("1");
}
// Set IOLOGIC params from FF params
iol->params[ctx->id("FF.INREGMODE")] = std::string("FF");
- iol->params[ctx->id("FF.REGSET")] = str_or_default(ci->params, ctx->id("REGSET"), "RESET");
- iol->params[ctx->id("SRMODE")] = str_or_default(ci->params, ctx->id("SRMODE"), "ASYNC");
- iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
- replace_port(ci, ctx->id("DI"), iol, id_PADDI);
- replace_port(ci, ctx->id("Q"), iol, id_INFF);
+ iol->params[ctx->id("FF.REGSET")] = str_or_default(ci->params, id_REGSET, "RESET");
+ iol->params[id_SRMODE] = str_or_default(ci->params, id_SRMODE, "ASYNC");
+ iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
+ replace_port(ci, id_DI, iol, id_PADDI);
+ replace_port(ci, id_Q, iol, id_INFF);
packed_cells.insert(cell.first);
continue;
}
}
if (mode != "input") {
- CellInfo *pio_t = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_T, true);
- CellInfo *pio_i = net_only_drives(ctx, ci->ports.at(ctx->id("Q")).net, is_trellis_io, id_I, true);
+ CellInfo *pio_t = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_T, true);
+ CellInfo *pio_i = net_only_drives(ctx, ci->ports.at(id_Q).net, is_trellis_io, id_I, true);
if (pio_t != nullptr || pio_i != nullptr) {
// Output or tristate FF
bool tri = (pio_t != nullptr);
@@ -2664,47 +2645,47 @@ class Ecp5Packer
iol = create_pio_iologic(pio, ci);
set_iologic_mode(iol, "IREG_OREG");
// Connection between FF and PIO
- replace_port(ci, ctx->id("Q"), iol, tri ? id_IOLTO : id_IOLDO);
+ replace_port(ci, id_Q, iol, tri ? id_IOLTO : id_IOLDO);
if (tri) {
if (!pio->ports.count(id_IOLTO)) {
pio->ports[id_IOLTO].name = id_IOLTO;
pio->ports[id_IOLTO].type = PORT_IN;
}
- pio->params[ctx->id("TRIMUX_TSREG")] = std::string("IOLTO");
+ pio->params[id_TRIMUX_TSREG] = std::string("IOLTO");
replace_port(pio, id_T, pio, id_IOLTO);
} else {
if (!pio->ports.count(id_IOLDO)) {
pio->ports[id_IOLDO].name = id_IOLDO;
pio->ports[id_IOLDO].type = PORT_IN;
}
- pio->params[ctx->id("DATAMUX_OREG")] = std::string("IOLDO");
+ pio->params[id_DATAMUX_OREG] = std::string("IOLDO");
replace_port(pio, id_I, pio, id_IOLDO);
}
- set_iologic_sclk(iol, ci, ctx->id("CLK"), false);
- set_iologic_lsr(iol, ci, ctx->id("LSR"), false);
+ set_iologic_sclk(iol, ci, id_CLK, false);
+ set_iologic_lsr(iol, ci, id_LSR, false);
// Handle CLK and CE muxes
- if (str_or_default(ci->params, ctx->id("CLKMUX")) == "INV")
- iol->params[ctx->id("CLKOMUX")] = std::string("INV");
- if (str_or_default(ci->params, ctx->id("CEMUX"), "CE") == "CE") {
- iol->params[ctx->id("CEOMUX")] = std::string("CEMUX");
- iol->params[ctx->id("CEMUX")] = std::string("CE");
- if (get_net_or_empty(ci, ctx->id("CE")) == nullptr)
- replace_port(ci, ctx->id("CE"), iol, ctx->id("CE"));
+ if (str_or_default(ci->params, id_CLKMUX) == "INV")
+ iol->params[id_CLKOMUX] = std::string("INV");
+ if (str_or_default(ci->params, id_CEMUX, "CE") == "CE") {
+ iol->params[id_CEOMUX] = std::string("CEMUX");
+ iol->params[id_CEMUX] = std::string("CE");
+ if (get_net_or_empty(ci, id_CE) == nullptr)
+ replace_port(ci, id_CE, iol, id_CE);
else
- disconnect_port(ctx, ci, ctx->id("CE"));
+ disconnect_port(ctx, ci, id_CE);
} else {
- iol->params[ctx->id("CEOMUX")] = std::string("1");
+ iol->params[id_CEOMUX] = std::string("1");
}
// FF params
iol->params[ctx->id(tri ? "TSREG.OUTREGMODE" : "OUTREG.OUTREGMODE")] = std::string("FF");
iol->params[ctx->id(tri ? "TSREG.REGSET" : "OUTREG.REGSET")] =
- str_or_default(ci->params, ctx->id("REGSET"), "RESET");
- iol->params[ctx->id("SRMODE")] = str_or_default(ci->params, ctx->id("SRMODE"), "ASYNC");
+ str_or_default(ci->params, id_REGSET, "RESET");
+ iol->params[id_SRMODE] = str_or_default(ci->params, id_SRMODE, "ASYNC");
// Data input
- replace_port(ci, ctx->id("DI"), iol, tri ? id_TSDATA0 : id_TXDATA0);
- iol->params[ctx->id("GSR")] = str_or_default(ci->params, ctx->id("GSR"), "DISABLED");
+ replace_port(ci, id_DI, iol, tri ? id_TSDATA0 : id_TXDATA0);
+ iol->params[id_GSR] = str_or_default(ci->params, id_GSR, "DISABLED");
packed_cells.insert(cell.first);
continue;
}
@@ -2724,26 +2705,25 @@ class Ecp5Packer
if (input == nullptr)
continue;
for (auto user : input->users) {
- if (!user.cell->attrs.count(ctx->id("BEL")))
+ if (!user.cell->attrs.count(id_BEL))
continue;
- Loc user_loc = ctx->getBelLocation(
- ctx->getBelByNameStr(user.cell->attrs.at(ctx->id("BEL")).as_string()));
+ Loc user_loc =
+ ctx->getBelLocation(ctx->getBelByNameStr(user.cell->attrs.at(id_BEL).as_string()));
for (auto bel : ctx->getBels()) {
if (ctx->getBelType(bel) != id_ECLKBRIDGECS)
continue;
loc = ctx->getBelLocation(bel);
if (loc.x == user_loc.x) {
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
goto eclkbridge_done;
}
}
}
if (input->driver.cell != nullptr) {
CellInfo *drv = input->driver.cell;
- if (!drv->attrs.count(ctx->id("BEL")))
+ if (!drv->attrs.count(id_BEL))
continue;
- Loc drv_loc =
- ctx->getBelLocation(ctx->getBelByNameStr(drv->attrs.at(ctx->id("BEL")).as_string()));
+ Loc drv_loc = ctx->getBelLocation(ctx->getBelByNameStr(drv->attrs.at(id_BEL).as_string()));
BelId closest;
int closest_x = -1; // aim for same side of chip
for (auto bel : ctx->getBels()) {
@@ -2757,7 +2737,7 @@ class Ecp5Packer
}
NPNR_ASSERT(closest != BelId());
loc = ctx->getBelLocation(closest);
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(closest).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(closest).str(ctx);
goto eclkbridge_done;
}
}
@@ -2766,7 +2746,7 @@ class Ecp5Packer
if (ctx->getBelType(bel) != id_ECLKBRIDGECS)
continue;
loc = ctx->getBelLocation(bel);
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
}
eclkbridge_done:
if (o != nullptr)
@@ -2787,7 +2767,7 @@ class Ecp5Packer
if (ci->type == id_IOLOGIC || ci->type == id_DQSBUFM) {
if (!ci->ports.count(id_ECLK) || ci->ports.at(id_ECLK).net == nullptr)
continue;
- BelId bel = ctx->getBelByNameStr(str_or_default(ci->attrs, ctx->id("BEL")));
+ BelId bel = ctx->getBelByNameStr(str_or_default(ci->attrs, id_BEL));
NPNR_ASSERT(bel != BelId());
Loc pioLoc = ctx->getBelLocation(bel);
if (ci->type == id_DQSBUFM)
@@ -2818,7 +2798,7 @@ class Ecp5Packer
// z-index of CLKDIVF must match index of ECLK
if (loc.z != eclk.first.second)
continue;
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
make_eclk(ci->ports.at(id_CLKI), ci, bel, eclk.first.first);
goto clkdiv_done;
}
@@ -2831,10 +2811,9 @@ class Ecp5Packer
const NetInfo *eclko = net_or_nullptr(ci, id_ECLKO);
if (eclki != nullptr && eclki->driver.cell != nullptr) {
if (eclki->driver.cell->type == id_ECLKBRIDGECS) {
- BelId bel = ctx->getBelByNameStr(eclki->driver.cell->attrs.at(ctx->id("BEL")).as_string());
+ BelId bel = ctx->getBelByNameStr(eclki->driver.cell->attrs.at(id_BEL).as_string());
Loc loc = ctx->getBelLocation(bel);
- ci->attrs[ctx->id("BEL")] =
- ctx->getBelName(ctx->getBelByLocation(Loc(loc.x, loc.y, 15))).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(ctx->getBelByLocation(Loc(loc.x, loc.y, 15))).str(ctx);
used_eclksyncb.insert(bel);
goto eclksync_done;
}
@@ -2843,14 +2822,14 @@ class Ecp5Packer
log_error("ECLKSYNCB '%s' has disconnected port ECLKO\n", ci->name.c_str(ctx));
for (auto user : eclko->users) {
if (user.cell->type == id_TRELLIS_ECLKBUF) {
- Loc eckbuf_loc = ctx->getBelLocation(
- ctx->getBelByNameStr(user.cell->attrs.at(ctx->id("BEL")).as_string()));
+ Loc eckbuf_loc =
+ ctx->getBelLocation(ctx->getBelByNameStr(user.cell->attrs.at(id_BEL).as_string()));
for (auto bel : ctx->getBels()) {
if (ctx->getBelType(bel) != id_ECLKSYNCB)
continue;
Loc loc = ctx->getBelLocation(bel);
if (loc.x == eckbuf_loc.x && loc.y == eckbuf_loc.y && loc.z == eckbuf_loc.z - 2) {
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
used_eclksyncb.insert(bel);
goto eclksync_done;
}
@@ -2859,7 +2838,7 @@ class Ecp5Packer
}
eclksync_done:
continue;
- } else if (ci->type == ctx->id("DDRDLLA")) {
+ } else if (ci->type == id_DDRDLLA) {
ci->type = id_DDRDLL; // transform from Verilog to Bel name
const NetInfo *clk = net_or_nullptr(ci, id_CLK);
if (clk == nullptr)
@@ -2871,9 +2850,9 @@ class Ecp5Packer
if (ddrdel != nullptr) {
for (auto &usr : ddrdel->users) {
const CellInfo *uc = usr.cell;
- if (uc->type != id_DQSBUFM || !uc->attrs.count(ctx->id("BEL")))
+ if (uc->type != id_DQSBUFM || !uc->attrs.count(id_BEL))
continue;
- BelId dqsb_bel = ctx->getBelByNameStr(uc->attrs.at(ctx->id("BEL")).as_string());
+ BelId dqsb_bel = ctx->getBelByNameStr(uc->attrs.at(id_BEL).as_string());
Loc dqsb_loc = ctx->getBelLocation(dqsb_bel);
if (dqsb_loc.x > 15)
right_bank_users = true;
@@ -2907,7 +2886,7 @@ class Ecp5Packer
if (eclk.first.first != ddrdll_bank)
continue;
log_info("Constraining DDRDLLA '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(bel));
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
make_eclk(ci->ports.at(id_CLK), ci, bel, eclk.first.first);
goto ddrdll_done;
}
@@ -2923,7 +2902,7 @@ class Ecp5Packer
if (ci->type == id_ECLKSYNCB) {
// **All** ECLKSYNCBs must be constrained
// Most will be dealt with above, but there might be some rogue cases
- if (ci->attrs.count(ctx->id("BEL")))
+ if (ci->attrs.count(id_BEL))
continue;
for (BelId bel : ctx->getBels()) {
if (ctx->getBelType(bel) != id_ECLKSYNCB)
@@ -2932,7 +2911,7 @@ class Ecp5Packer
if (used_eclksyncb.count(bel))
continue;
log_info("Constraining ECLKSYNCB '%s' to bel '%s'\n", ctx->nameOf(ci), ctx->nameOfBel(bel));
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(bel).str(ctx);
goto eclksync_ii_done;
}
if (0) {
@@ -2946,7 +2925,7 @@ class Ecp5Packer
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (ci->type == id_CLKDIVF) {
- if (ci->attrs.count(ctx->id("BEL")))
+ if (ci->attrs.count(id_BEL))
continue;
// Case of a CLKDIVF driven by an ECLKSYNC constrained above; without the input being used elsewhere as
// an edge clock
@@ -2954,9 +2933,9 @@ class Ecp5Packer
if (clki == nullptr || clki->driver.cell == nullptr)
continue;
CellInfo *drv = clki->driver.cell;
- if (drv->type != id_ECLKSYNCB || !drv->attrs.count(ctx->id("BEL")))
+ if (drv->type != id_ECLKSYNCB || !drv->attrs.count(id_BEL))
continue;
- BelId bel = ctx->getBelByNameStr(drv->attrs.at(ctx->id("BEL")).as_string());
+ BelId bel = ctx->getBelByNameStr(drv->attrs.at(id_BEL).as_string());
// Find a CLKDIVF that is routeable from the ECLKSYNC
std::queue<WireId> visit;
visit.push(ctx->getBelPinWire(bel, id_ECLKO));
@@ -2966,7 +2945,7 @@ class Ecp5Packer
for (BelPin bp : ctx->getWireBelPins(cursor)) {
if (ctx->getBelType(bp.bel) != id_CLKDIVF || bp.pin != id_CLKI)
continue;
- ci->attrs[ctx->id("BEL")] = ctx->getBelName(bp.bel).str(ctx);
+ ci->attrs[id_BEL] = ctx->getBelName(bp.bel).str(ctx);
log_info("Constraining CLKDIVF '%s' to bel '%s' based on ECLKSYNCB.\n", ctx->nameOf(ci),
ctx->nameOfBel(bp.bel));
goto clkdiv_ii_done;
@@ -3076,7 +3055,7 @@ class Ecp5Packer
for (auto cell : changed_cells) {
CellInfo *ci = ctx->cells.at(cell).get();
if (ci->type == id_CLKDIVF) {
- std::string div = str_or_default(ci->params, ctx->id("DIV"), "2.0");
+ std::string div = str_or_default(ci->params, id_DIV, "2.0");
double ratio;
if (div == "2.0")
ratio = 1 / 2.0;
@@ -3098,17 +3077,17 @@ class Ecp5Packer
continue;
log_info(" Input frequency of PLL '%s' is constrained to %.1f MHz\n", ci->name.c_str(ctx),
MHz(period_in));
- double period_in_div = period_in * int_or_default(ci->params, ctx->id("CLKI_DIV"), 1);
- std::string path = str_or_default(ci->params, ctx->id("FEEDBK_PATH"), "CLKOP");
- int feedback_div = int_or_default(ci->params, ctx->id("CLKFB_DIV"), 1);
+ double period_in_div = period_in * int_or_default(ci->params, id_CLKI_DIV, 1);
+ std::string path = str_or_default(ci->params, id_FEEDBK_PATH, "CLKOP");
+ int feedback_div = int_or_default(ci->params, id_CLKFB_DIV, 1);
if (path == "CLKOP" || path == "INT_OP")
- feedback_div *= int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1);
+ feedback_div *= int_or_default(ci->params, id_CLKOP_DIV, 1);
else if (path == "CLKOS" || path == "INT_OS")
- feedback_div *= int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1);
+ feedback_div *= int_or_default(ci->params, id_CLKOS_DIV, 1);
else if (path == "CLKOS2" || path == "INT_OS2")
- feedback_div *= int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1);
+ feedback_div *= int_or_default(ci->params, id_CLKOS2_DIV, 1);
else if (path == "CLKOS3" || path == "INT_OS3")
- feedback_div *= int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1);
+ feedback_div *= int_or_default(ci->params, id_CLKOS3_DIV, 1);
else {
log_info(" Unable to determine output frequencies for PLL '%s' with FEEDBK_PATH=%s\n",
ci->name.c_str(ctx), path.c_str());
@@ -3120,12 +3099,12 @@ class Ecp5Packer
log_info(" Derived VCO frequency %.1f MHz of PLL '%s' is out of legal range [400MHz, "
"800MHz]\n",
vco_freq, ci->name.c_str(ctx));
- set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, ctx->id("CLKOP_DIV"), 1));
- set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, ctx->id("CLKOS_DIV"), 1));
- set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, ctx->id("CLKOS2_DIV"), 1));
- set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, ctx->id("CLKOS3_DIV"), 1));
+ set_period(ci, id_CLKOP, vco_period * int_or_default(ci->params, id_CLKOP_DIV, 1));
+ set_period(ci, id_CLKOS, vco_period * int_or_default(ci->params, id_CLKOS_DIV, 1));
+ set_period(ci, id_CLKOS2, vco_period * int_or_default(ci->params, id_CLKOS2_DIV, 1));
+ set_period(ci, id_CLKOS3, vco_period * int_or_default(ci->params, id_CLKOS3_DIV, 1));
} else if (ci->type == id_OSCG) {
- int div = int_or_default(ci->params, ctx->id("DIV"), 128);
+ int div = int_or_default(ci->params, id_DIV, 128);
set_period(ci, id_OSC, delay_t((1.0e6 / (2.0 * 155)) * div));
}
}
@@ -3137,8 +3116,8 @@ class Ecp5Packer
// Check for legacy-style JSON (use CEMUX as a clue) and error out, avoiding a confusing assertion failure
// later
for (auto &cell : ctx->cells) {
- if (is_ff(ctx, cell.second.get()) && cell.second->params.count(ctx->id("CEMUX")) &&
- !cell.second->params[ctx->id("CEMUX")].is_string)
+ if (is_ff(ctx, cell.second.get()) && cell.second->params.count(id_CEMUX) &&
+ !cell.second->params[id_CEMUX].is_string)
log_error("Found netlist using legacy-style JSON parameter values, please update your Yosys.\n");
}
}
@@ -3199,7 +3178,7 @@ bool Arch::pack()
Ecp5Packer(ctx).pack();
log_info("Checksum: 0x%08x\n", ctx->checksum());
assignArchInfo();
- ctx->settings[ctx->id("pack")] = 1;
+ ctx->settings[id_pack] = 1;
archInfoToAttributes();
return true;
} catch (log_execution_error_exception) {
@@ -3233,24 +3212,24 @@ void Arch::assignArchInfo()
ci->sliceInfo.clkmux = id(str_or_default(ci->params, id_CLKMUX, "CLK"));
ci->sliceInfo.lsrmux = id(str_or_default(ci->params, id_LSRMUX, "LSR"));
ci->sliceInfo.srmode = id(str_or_default(ci->params, id_SRMODE, "LSR_OVER_CE"));
- std::string mode = str_or_default(ci->params, id("MODE"), "LOGIC");
+ std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
ci->sliceInfo.is_carry = (mode == "CCU2");
ci->sliceInfo.is_memory = (mode == "DPRAM" || mode == "RAMW");
- ci->sliceInfo.sd0 = std::stoi(str_or_default(ci->params, id("REG0_SD"), "0"));
- ci->sliceInfo.sd1 = std::stoi(str_or_default(ci->params, id("REG1_SD"), "0"));
+ ci->sliceInfo.sd0 = std::stoi(str_or_default(ci->params, id_REG0_SD, "0"));
+ ci->sliceInfo.sd1 = std::stoi(str_or_default(ci->params, id_REG1_SD, "0"));
ci->sliceInfo.has_l6mux = false;
if (ci->ports.count(id_FXA) && ci->ports[id_FXA].net != nullptr &&
ci->ports[id_FXA].net->driver.port == id_OFX0)
ci->sliceInfo.has_l6mux = true;
} else if (ci->type == id_DP16KD) {
- ci->ramInfo.is_pdp = (int_or_default(ci->params, id("DATA_WIDTH_A"), 0) == 36);
+ ci->ramInfo.is_pdp = (int_or_default(ci->params, id_DATA_WIDTH_A, 0) == 36);
// Output register mode (REGMODE_{A,B}). Valid options are 'NOREG' and 'OUTREG'.
- std::string regmode_a = str_or_default(ci->params, id("REGMODE_A"), "NOREG");
+ std::string regmode_a = str_or_default(ci->params, id_REGMODE_A, "NOREG");
if (regmode_a != "NOREG" && regmode_a != "OUTREG")
log_error("DP16KD %s has invalid REGMODE_A configuration '%s'\n", ci->name.c_str(this),
regmode_a.c_str());
- std::string regmode_b = str_or_default(ci->params, id("REGMODE_B"), "NOREG");
+ std::string regmode_b = str_or_default(ci->params, id_REGMODE_B, "NOREG");
if (regmode_b != "NOREG" && regmode_b != "OUTREG")
log_error("DP16KD %s has invalid REGMODE_B configuration '%s'\n", ci->name.c_str(this),
regmode_b.c_str());
@@ -3326,7 +3305,7 @@ void Arch::assignArchInfo()
}
}
for (auto &net : nets) {
- net.second->is_global = bool_or_default(net.second->attrs, id("ECP5_IS_GLOBAL"));
+ net.second->is_global = bool_or_default(net.second->attrs, id_ECP5_IS_GLOBAL);
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 11:13:44 +0000