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author | David Shah <davey1576@gmail.com> | 2018-08-08 19:08:43 +0200 |
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committer | David Shah <davey1576@gmail.com> | 2018-08-08 19:08:43 +0200 |
commit | a3ae3f97913c291dbe36a49b1a20388156943abc (patch) | |
tree | aa18634d3ea82650dd6e19330bb1ed9c87f472c3 /ecp5/trellis_import.py | |
parent | abf5ea84b9700c72a19327cda1000db0f80b34e0 (diff) | |
download | nextpnr-a3ae3f97913c291dbe36a49b1a20388156943abc.tar.gz nextpnr-a3ae3f97913c291dbe36a49b1a20388156943abc.tar.bz2 nextpnr-a3ae3f97913c291dbe36a49b1a20388156943abc.zip |
ecp5: Update to use const IdStrings in place of PortPin/BelType
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ecp5/trellis_import.py')
-rwxr-xr-x | ecp5/trellis_import.py | 26 |
1 files changed, 12 insertions, 14 deletions
diff --git a/ecp5/trellis_import.py b/ecp5/trellis_import.py index 99e9078f..7c7c9e15 100755 --- a/ecp5/trellis_import.py +++ b/ecp5/trellis_import.py @@ -11,7 +11,7 @@ tiletype_names = dict() parser = argparse.ArgumentParser(description="import ECP5 routing and bels from Project Trellis") parser.add_argument("device", type=str, help="target device") -parser.add_argument("-p", "--portspins", type=str, help="path to portpins.inc") +parser.add_argument("-p", "--constids", type=str, help="path to constids.inc") args = parser.parse_args() @@ -28,7 +28,7 @@ def get_tiletype_index(name): return idx -portpins = dict() +constids = dict() class BinaryBlobAssembler: @@ -78,12 +78,6 @@ class BinaryBlobAssembler: def pop(self): print("pop") -bel_types = { - "NONE": 0, - "SLICE": 1, - "PIO": 2 -} - def get_bel_index(ddrg, loc, name): loctype = ddrg.locationTypes[ddrg.typeAtLocation[loc]] idx = 0 @@ -181,7 +175,7 @@ def write_database(dev_name, chip, ddrg, endianness): for bp in wire.belPins: write_loc(bp.bel.rel, "rel_bel_loc") bba.u32(bp.bel.id, "bel_index") - bba.u32(portpins[ddrg.to_str(bp.pin)], "port") + bba.u32(constids[ddrg.to_str(bp.pin)], "port") bba.l("loc%d_wires" % idx, "WireInfoPOD") for wire_idx in range(len(loctype.wires)): wire = loctype.wires[wire_idx] @@ -200,13 +194,13 @@ def write_database(dev_name, chip, ddrg, endianness): for pin in bel.wires: write_loc(pin.wire.rel, "rel_wire_loc") bba.u32(pin.wire.id, "wire_index") - bba.u32(portpins[ddrg.to_str(pin.pin)], "port") + bba.u32(constids[ddrg.to_str(pin.pin)], "port") bba.u32(int(pin.dir), "dir") bba.l("loc%d_bels" % idx, "BelInfoPOD") for bel_idx in range(len(loctype.bels)): bel = loctype.bels[bel_idx] bba.s(ddrg.to_str(bel.name), "name") - bba.u32(bel_types[ddrg.to_str(bel.type)], "type") + bba.u32(constids[ddrg.to_str(bel.type)], "type") bba.u32(bel.z, "z") bba.u32(len(bel.wires), "num_bel_wires") bba.r("loc%d_bel%d_wires" % (idx, bel_idx), "bel_wires") @@ -305,7 +299,7 @@ def main(): args = parser.parse_args() # Read port pin file - with open(args.portspins) as f: + with open(args.constids) as f: for line in f: line = line.replace("(", " ") line = line.replace(")", " ") @@ -314,8 +308,12 @@ def main(): continue assert len(line) == 2 assert line[0] == "X" - idx = len(portpins) + 1 - portpins[line[1]] = idx + idx = len(constids) + 1 + constids[line[1]] = idx + + + constids["SLICE"] = constids["TRELLIS_SLICE"] + constids["PIO"] = constids["TRELLIS_IO"] # print("Initialising chip...") chip = pytrellis.Chip(dev_names[args.device]) |