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author | Adam Greig <adam@adamgreig.com> | 2021-03-31 02:20:09 +0100 |
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committer | Adam Greig <adam@adamgreig.com> | 2021-04-29 02:23:43 +0100 |
commit | d4c688297c1f4d0e70412e6aacdfd58d6b065749 (patch) | |
tree | 2d583b44bf8dc65f0407bf538d5960e0f49ed238 /ecp5/pack.cc | |
parent | 9538954cc67f8379cd46ee5e066c32f5dbbc5594 (diff) | |
download | nextpnr-d4c688297c1f4d0e70412e6aacdfd58d6b065749.tar.gz nextpnr-d4c688297c1f4d0e70412e6aacdfd58d6b065749.tar.bz2 nextpnr-d4c688297c1f4d0e70412e6aacdfd58d6b065749.zip |
Add relative constraints to position MULT18X18D near connected ALU54B.
Diffstat (limited to 'ecp5/pack.cc')
-rw-r--r-- | ecp5/pack.cc | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/ecp5/pack.cc b/ecp5/pack.cc index aa7fdd22..ac16536d 100644 --- a/ecp5/pack.cc +++ b/ecp5/pack.cc @@ -1573,6 +1573,30 @@ class Ecp5Packer autocreate_empty_port(ci, ctx->id(port + std::to_string(i))); for (int i = 0; i < 11; i++) autocreate_empty_port(ci, ctx->id("OP" + std::to_string(i))); + + // Find the MULT18X18Ds feeding this ALU54B's inputs and + // constrain them to the ALU. + for (auto port : {id_MA0, id_MB0}) { + CellInfo *mult = net_driven_by( + ctx, ci->ports.at(port).net, + [](const Context *ctx, const CellInfo *cell) { + return cell->type == id_MULT18X18D; + }, id_P0 + ); + if(mult != nullptr) { + if(port == id_MA0) { + mult->constr_x = mult->constr_z = -3; + } else if(port == id_MB0) { + mult->constr_x = mult->constr_z = -2; + } + mult->constr_y = 0; + mult->constr_parent = ci; + ci->constr_children.push_back(mult); + log_info("DSP: Constraining MULT18X18D '%s' to ALU54B '%s' port %s\n", + mult->name.c_str(ctx), cell.first.c_str(ctx), + ctx->nameOf(port)); + } + } } } } |