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| author | David Shah <dave@ds0.me> | 2019-08-31 20:50:54 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-31 20:50:54 +0100 |
| commit | c0b7379e8672b6263152d5e340e62f22179fdc8b (patch) | |
| tree | 4fda0724a855551efcd188fff23e7e3a66ffdbe8 /ecp5/bitstream.cc | |
| parent | cce5cb65c108140d997eb60ffd92a9fc7ad02a5c (diff) | |
| parent | 04be9a71f961feec668dd94343a6f3bb41d31927 (diff) | |
| download | nextpnr-c0b7379e8672b6263152d5e340e62f22179fdc8b.tar.gz nextpnr-c0b7379e8672b6263152d5e340e62f22179fdc8b.tar.bz2 nextpnr-c0b7379e8672b6263152d5e340e62f22179fdc8b.zip | |
Merge pull request #321 from YosysHQ/ecp5-dcc
ecp5: Add support for clock gating with DCCA
Diffstat (limited to 'ecp5/bitstream.cc')
| -rw-r--r-- | ecp5/bitstream.cc | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index c5a04a8d..f010d7dd 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -892,7 +892,35 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex if (datamux_mddr != "PADDO") cc.tiles[pic_tile].add_enum(pio + ".DATAMUX_MDDR", datamux_mddr); } else if (ci->type == ctx->id("DCCA")) { - // Nothing to do + const NetInfo *cen = get_net_or_empty(ci, ctx->id("CE")); + if (cen != nullptr) { + std::string belname = ctx->locInfo(bel)->bel_data[bel.index].name.get(); + Loc loc = ctx->getBelLocation(bel); + TileGroup tg; + switch (belname[0]) { + case 'B': + tg.tiles.push_back( + ctx->getTileByTypeAndLocation(loc.y, loc.x, std::set<std::string>{"BMID_0H", "BMID_0V"})); + tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, + std::set<std::string>{"BMID_2", "BMID_2V"})); + break; + case 'T': + tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "TMID_0")); + tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x + 1, "TMID_1")); + break; + case 'L': + tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "LMID_0")); + break; + case 'R': + tg.tiles.push_back(ctx->getTileByTypeAndLocation(loc.y, loc.x, "RMID_0")); + break; + default: + NPNR_ASSERT_FALSE("bad DCC for gating"); + break; + } + tg.config.add_enum(std::string("DCC_") + belname[0] + belname.substr(4) + ".MODE", "DCCA"); + cc.tilegroups.push_back(tg); + } } else if (ci->type == ctx->id("DP16KD")) { TileGroup tg; Loc loc = ctx->getBelLocation(ci->bel); |