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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-05 16:46:24 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-05 16:46:24 +0200 |
| commit | 6c8319e29a68d8d54b747e95c3f4a8df8a14d3ba (patch) | |
| tree | 8b289ec41872e8f907e001500ff2d237c9350342 /ecp5/bitstream.cc | |
| parent | b3acd8095fdcffe0dc116218d824a6c03562b69e (diff) | |
| parent | 736f2a07175b85a94ca77cb930be528a4c7671ea (diff) | |
| download | nextpnr-6c8319e29a68d8d54b747e95c3f4a8df8a14d3ba.tar.gz nextpnr-6c8319e29a68d8d54b747e95c3f4a8df8a14d3ba.tar.bz2 nextpnr-6c8319e29a68d8d54b747e95c3f4a8df8a14d3ba.zip | |
Merge pull request #37 from YosysHQ/ngapi
API change: Use CellInfo* and NetInfo* as cell/net handles
Diffstat (limited to 'ecp5/bitstream.cc')
| -rw-r--r-- | ecp5/bitstream.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/ecp5/bitstream.cc b/ecp5/bitstream.cc index f12e09b2..a1edf9e5 100644 --- a/ecp5/bitstream.cc +++ b/ecp5/bitstream.cc @@ -163,7 +163,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex // Add all set, configurable pips to the config for (auto pip : ctx->getPips()) { - if (ctx->getBoundPipNet(pip) != IdString()) { + if (ctx->getBoundPipNet(pip) != nullptr) { if (ctx->getPipClass(pip) == 0) { // ignore fixed pips std::string tile = ctx->getPipTilename(pip); std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); @@ -244,9 +244,9 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex cc.tiles[tname].add_enum(slice + ".REG1.REGSET", str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET")); cc.tiles[tname].add_enum(slice + ".CEMUX", str_or_default(ci->params, ctx->id("CEMUX"), "1")); - IdString lsrnet; + NetInfo *lsrnet = nullptr; if (ci->ports.find(ctx->id("LSR")) != ci->ports.end() && ci->ports.at(ctx->id("LSR")).net != nullptr) - lsrnet = ci->ports.at(ctx->id("LSR")).net->name; + lsrnet = ci->ports.at(ctx->id("LSR")).net; if (ctx->getBoundWireNet(ctx->getWireByName( ctx->id(fmt_str("X" << bel.location.x << "/Y" << bel.location.y << "/LSR0")))) == lsrnet) { cc.tiles[tname].add_enum("LSR0.SRMODE", str_or_default(ci->params, ctx->id("SRMODE"), "LSR_OVER_CE")); |