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authorDavid Shah <davey1576@gmail.com>2018-08-08 14:37:59 +0200
committerDavid Shah <davey1576@gmail.com>2018-08-08 14:37:59 +0200
commitbf42e525cb7ab6ae071b16dfeca55194878be69c (patch)
treec9282e371fc57a71550e1dcca0ae9e38724d5bf4 /ecp5/arch.cc
parenta0994d515454a696c98602980b298ee61aa03f4e (diff)
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Arch API: New specification for timing port classes
Signed-off-by: David Shah <davey1576@gmail.com>
Diffstat (limited to 'ecp5/arch.cc')
-rw-r--r--ecp5/arch.cc7
1 files changed, 4 insertions, 3 deletions
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index de3abd44..12707a03 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -495,9 +495,10 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
return false;
}
-IdString Arch::getPortClock(const CellInfo *cell, IdString port) const { return IdString(); }
-
-bool Arch::isClockPort(const CellInfo *cell, IdString port) const { return false; }
+TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const
+{
+ return TMG_IGNORE;
+}
bool Arch::isIOCell(const CellInfo *cell) const { return cell->type == id("TRELLIS_IO"); }