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| author | David Shah <davey1576@gmail.com> | 2018-08-08 19:23:47 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-08 19:23:47 +0200 |
| commit | cd4e761bb799ca99f02d3aa177961af28a93f2d8 (patch) | |
| tree | a6424fb4ea70b868efb1375bb9cf3db992e3059c /docs | |
| parent | 2390f7f59c05870845da349536cb384964cdb874 (diff) | |
| parent | 751335977fe7d69b23f6110ec4938408ec7a7ff8 (diff) | |
| download | nextpnr-cd4e761bb799ca99f02d3aa177961af28a93f2d8.tar.gz nextpnr-cd4e761bb799ca99f02d3aa177961af28a93f2d8.tar.bz2 nextpnr-cd4e761bb799ca99f02d3aa177961af28a93f2d8.zip | |
Merge pull request #44 from YosysHQ/improve_timing_spec
Speed up budget allocator using topographical ordering and update cell timing API
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/archapi.md | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/docs/archapi.md b/docs/archapi.md index 222b9f78..3a2b5efb 100644 --- a/docs/archapi.md +++ b/docs/archapi.md @@ -455,13 +455,11 @@ Cell Delay Methods Returns the delay for the specified path through a cell in the `&delay` argument. The method returns false if there is no timing relationship from `fromPort` to `toPort`. -### IdString getPortClock(const CellInfo \*cell, IdString port) const +### TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, IdString &clockPort) const -Returns the clock input port for the specified output port. - -### bool isClockPort(const CellInfo \*cell, IdString port) const - -Returns true if the specified port is a clock input. +Return the _timing port class_ of a port. This can be a register or combinational input or output; clock input or +output; general startpoint or endpoint; or a port ignored for timing purposes. For register ports, clockPort is set +to the associated clock port. Placer Methods -------------- |