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| author | Sylvain Munaut <tnt@246tNt.com> | 2020-03-29 10:27:42 +0200 |
|---|---|---|
| committer | Sylvain Munaut <tnt@246tNt.com> | 2020-03-29 10:27:42 +0200 |
| commit | bd68d6035cfb4b49bc7a2183a8ce751c3b7c5b57 (patch) | |
| tree | 6c77696798a669a784d37e2a41def9d98b3c3822 /docs | |
| parent | a3ede0293a50c910e7d96319b2084d50f2501a6b (diff) | |
| download | nextpnr-bd68d6035cfb4b49bc7a2183a8ce751c3b7c5b57.tar.gz nextpnr-bd68d6035cfb4b49bc7a2183a8ce751c3b7c5b57.tar.bz2 nextpnr-bd68d6035cfb4b49bc7a2183a8ce751c3b7c5b57.zip | |
ice40: Fix output register timing analysis for registered output enable
Wrong bits were being tested. [5:4] is what's controlling the output
enable path.
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Diffstat (limited to 'docs')
0 files changed, 0 insertions, 0 deletions