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| author | David Shah <dave@ds0.me> | 2021-01-28 16:10:22 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-01-28 16:10:22 +0000 |
| commit | 15b2852b916c1299dfc1d91a217de3060701bfbe (patch) | |
| tree | 8e7ffbce4b7d253f05d0bb58ea6430aae8e1b065 /docs/archapi.md | |
| parent | 0d9790421699a22fc6a5962b41910c3b7d089353 (diff) | |
| parent | 94e8847d674388c3c8ac663fa4912bb8029b2951 (diff) | |
| download | nextpnr-15b2852b916c1299dfc1d91a217de3060701bfbe.tar.gz nextpnr-15b2852b916c1299dfc1d91a217de3060701bfbe.tar.bz2 nextpnr-15b2852b916c1299dfc1d91a217de3060701bfbe.zip | |
Merge pull request #556 from YosysHQ/dave/cleanup
General opportunistic cleanup
Diffstat (limited to 'docs/archapi.md')
| -rw-r--r-- | docs/archapi.md | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/docs/archapi.md b/docs/archapi.md index 3de6c132..a9c38589 100644 --- a/docs/archapi.md +++ b/docs/archapi.md @@ -320,8 +320,8 @@ Get the source wire for a pip. Get the destination wire for a pip. -Bi-directional switches (transfer gates) are modelled using two -antiparallel pips. +Bi-directional switches (transfer gates) are modeled using two +anti-parallel pips. ### DelayInfo getPipDelay(PipId pip) const @@ -378,8 +378,8 @@ This should return a low upper bound for the fastest route from `src` to `dst`. Or in other words it should assume an otherwise unused chip (thus "fastest route"). But it only produces an estimate for that fastest route, not an exact -result, and for that estimate it is considered more accaptable to return a -slightly too high result and it is considered less accaptable to return a +result, and for that estimate it is considered more acceptable to return a +slightly too high result and it is considered less acceptable to return a too low result (thus "low upper bound"). ### delay\_t predictDelay(const NetInfo \*net\_info, const PortRef &sink) const |