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authorgatecat <gatecat@ds0.me>2021-06-01 16:51:18 +0100
committergatecat <gatecat@ds0.me>2021-06-02 14:27:56 +0100
commit579b98c5963c2b86d191d481a2147a663a8196dd (patch)
treea37baaeac305fbb9d3f7db98ccda8a1708ac234c /common/timing.cc
parentff72454f8391ab4785fa8314f3efbbea96c30422 (diff)
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Use hashlib for core netlist structures
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'common/timing.cc')
-rw-r--r--common/timing.cc14
1 files changed, 7 insertions, 7 deletions
diff --git a/common/timing.cc b/common/timing.cc
index ef5977de..b68ca35c 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -52,17 +52,17 @@ void TimingAnalyser::run()
void TimingAnalyser::init_ports()
{
// Per cell port structures
- for (auto cell : sorted(ctx->cells)) {
- CellInfo *ci = cell.second;
- for (auto port : sorted_ref(ci->ports)) {
+ for (auto &cell : ctx->cells) {
+ CellInfo *ci = cell.second.get();
+ for (auto &port : ci->ports) {
auto &data = ports[CellPortKey(ci->name, port.first)];
data.type = port.second.type;
data.cell_port = CellPortKey(ci->name, port.first);
}
}
// Cell port to net port mapping
- for (auto net : sorted(ctx->nets)) {
- NetInfo *ni = net.second;
+ for (auto &net : ctx->nets) {
+ NetInfo *ni = net.second.get();
if (ni->driver.cell != nullptr)
ports[CellPortKey(ni->driver)].net_port = NetPortKey(ni->name);
for (size_t i = 0; i < ni->users.size(); i++)
@@ -138,8 +138,8 @@ void TimingAnalyser::get_cell_delays()
void TimingAnalyser::get_route_delays()
{
- for (auto net : sorted(ctx->nets)) {
- NetInfo *ni = net.second;
+ for (auto &net : ctx->nets) {
+ NetInfo *ni = net.second.get();
if (ni->driver.cell == nullptr || ni->driver.cell->bel == BelId())
continue;
for (auto &usr : ni->users) {