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authorClifford Wolf <clifford@clifford.at>2018-06-18 14:06:37 +0200
committerClifford Wolf <clifford@clifford.at>2018-06-18 14:06:37 +0200
commit8ee149f4fcb66cb61aa729263448c0935fb4d2ad (patch)
tree545282eae56973d52a88600d1cf82196970ecad7 /common/pybindings.cc
parentad18cdb08787c4ecc88edaec353a96f59135c62d (diff)
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Rename Design to Context, derive from Arch instead of instantiating
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'common/pybindings.cc')
-rw-r--r--common/pybindings.cc17
1 files changed, 8 insertions, 9 deletions
diff --git a/common/pybindings.cc b/common/pybindings.cc
index 3621d27a..4c10939a 100644
--- a/common/pybindings.cc
+++ b/common/pybindings.cc
@@ -47,7 +47,7 @@ bool operator==(const PortRef &a, const PortRef &b)
}
// Load a JSON file into a design
-void parse_json_shim(std::string filename, Design &d)
+void parse_json_shim(std::string filename, Context &d)
{
std::ifstream inf(filename);
if (!inf)
@@ -57,9 +57,9 @@ void parse_json_shim(std::string filename, Design &d)
}
// Create a new Chip and load design from json file
-Design load_design_shim(std::string filename, ArchArgs args)
+Context load_design_shim(std::string filename, ArchArgs args)
{
- Design d(args);
+ Context d(args);
parse_json_shim(filename, d);
return d;
}
@@ -113,13 +113,12 @@ BOOST_PYTHON_MODULE(MODULE_NAME)
WRAP_MAP(decltype(CellInfo::ports), "IdPortMap");
// WRAP_MAP(decltype(CellInfo::pins), "IdIdMap");
- class_<Design, Design *>("Design", no_init)
- .def_readwrite("chip", &Design::chip)
- .def_readwrite("nets", &Design::nets)
- .def_readwrite("cells", &Design::cells);
+ class_<Context, Context *>("Context", no_init)
+ .def_readwrite("nets", &Context::nets)
+ .def_readwrite("cells", &Context::cells);
- WRAP_MAP(decltype(Design::nets), "IdNetMap");
- WRAP_MAP(decltype(Design::cells), "IdCellMap");
+ WRAP_MAP(decltype(Context::nets), "IdNetMap");
+ WRAP_MAP(decltype(Context::cells), "IdCellMap");
def("parse_json", parse_json_shim);
def("load_design", load_design_shim);