Get rid of old iCE40 id_ Arch members

Signed-off-by: Clifford Wolf <clifford@clifford.at>

6 files changed, 36 insertions, 59 deletions

diff --git a/ice40/arch.cc b/ice40/arch.cc
index 328be747..0c078f0e 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -92,29 +92,6 @@ Arch::Arch(ArchArgs args) : args(args)
     wire_to_net.resize(chip_info->num_wires);
     pip_to_net.resize(chip_info->num_pips);
     switches_locked.resize(chip_info->num_switches);
-
-    // Initialise regularly used IDStrings for performance
-    id_glb_buf_out = id("GLOBAL_BUFFER_OUTPUT");
-    id_icestorm_lc = id("ICESTORM_LC");
-    id_sb_io = id("SB_IO");
-    id_sb_gb = id("SB_GB");
-    id_cen = id("CEN");
-    id_clk = id("CLK");
-    id_sr = id("SR");
-    id_i0 = id("I0");
-    id_i1 = id("I1");
-    id_i2 = id("I2");
-    id_i3 = id("I3");
-    id_dff_en = id("DFF_ENABLE");
-    id_carry_en = id("CARRY_ENABLE");
-    id_neg_clk = id("NEG_CLK");
-    id_cin = id("CIN");
-    id_cout = id("COUT");
-    id_o = id("O");
-    id_lo = id("LO");
-    id_icestorm_ram = id("ICESTORM_RAM");
-    id_rclk = id("RCLK");
-    id_wclk = id("WCLK");
 }
 
 // -----------------------------------------------------------------------
@@ -553,7 +530,7 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
 bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
 {
     const auto &driver = net_info->driver;
-    if (driver.port == id_cout && sink.port == id_cin) {
+    if (driver.port == id_COUT && sink.port == id_CIN) {
         auto driver_loc = getBelLocation(driver.cell->bel);
         auto sink_loc = getBelLocation(sink.cell->bel);
         if (driver_loc.y == sink_loc.y)
@@ -795,23 +772,23 @@ bool Arch::getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort
 
 IdString Arch::getPortClock(const CellInfo *cell, IdString port) const
 {
-    if (cell->type == id_icestorm_lc && cell->lcInfo.dffEnable) {
-        if (port != id_lo && port != id_cin && port != id_cout)
-            return id_clk;
-    } else if (cell->type == id_icestorm_ram) {
+    if (cell->type == id_ICESTORM_LC && cell->lcInfo.dffEnable) {
+        if (port != id_LO && port != id_CIN && port != id_COUT)
+            return id_CLK;
+    } else if (cell->type == id_ICESTORM_RAM) {
         if (port.str(this)[0] == 'R')
-            return id_rclk;
+            return id_RCLK;
         else
-            return id_wclk;
+            return id_WCLK;
     }
     return IdString();
 }
 
 bool Arch::isClockPort(const CellInfo *cell, IdString port) const
 {
-    if (cell->type == id("ICESTORM_LC") && port == id("CLK"))
+    if (cell->type == id_ICESTORM_LC && port == id_CLK)
         return true;
-    if (cell->type == id("ICESTORM_RAM") && (port == id("RCLK") || (port == id("WCLK"))))
+    if (cell->type == id_ICESTORM_RAM && (port == id_RCLK || port == id_WCLK))
         return true;
     return false;
 }
@@ -820,7 +797,7 @@ bool Arch::isGlobalNet(const NetInfo *net) const
 {
     if (net == nullptr)
         return false;
-    return net->driver.cell != nullptr && net->driver.port == id_glb_buf_out;
+    return net->driver.cell != nullptr && net->driver.port == id_GLOBAL_BUFFER_OUTPUT;
 }
 
 // Assign arch arg info
@@ -849,20 +826,20 @@ void Arch::assignCellInfo(CellInfo *cell)
 {
     cell->belType = cell->type;
     if (cell->type == id_ICESTORM_LC) {
-        cell->lcInfo.dffEnable = bool_or_default(cell->params, id_dff_en);
-        cell->lcInfo.carryEnable = bool_or_default(cell->params, id_carry_en);
-        cell->lcInfo.negClk = bool_or_default(cell->params, id_neg_clk);
-        cell->lcInfo.clk = get_net_or_empty(cell, id_clk);
-        cell->lcInfo.cen = get_net_or_empty(cell, id_cen);
-        cell->lcInfo.sr = get_net_or_empty(cell, id_sr);
+        cell->lcInfo.dffEnable = bool_or_default(cell->params, id_DFF_ENABLE);
+        cell->lcInfo.carryEnable = bool_or_default(cell->params, id_CARRY_ENABLE);
+        cell->lcInfo.negClk = bool_or_default(cell->params, id_NEG_CLK);
+        cell->lcInfo.clk = get_net_or_empty(cell, id_CLK);
+        cell->lcInfo.cen = get_net_or_empty(cell, id_CEN);
+        cell->lcInfo.sr = get_net_or_empty(cell, id_SR);
         cell->lcInfo.inputCount = 0;
-        if (get_net_or_empty(cell, id_i0))
+        if (get_net_or_empty(cell, id_I0))
             cell->lcInfo.inputCount++;
-        if (get_net_or_empty(cell, id_i1))
+        if (get_net_or_empty(cell, id_I1))
             cell->lcInfo.inputCount++;
-        if (get_net_or_empty(cell, id_i2))
+        if (get_net_or_empty(cell, id_I2))
             cell->lcInfo.inputCount++;
-        if (get_net_or_empty(cell, id_i3))
+        if (get_net_or_empty(cell, id_I3))
             cell->lcInfo.inputCount++;
     }
 }
diff --git a/ice40/arch.h b/ice40/arch.h
index 69d3e2b9..62a637ae 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -437,7 +437,7 @@ struct Arch : BaseCtx
         NPNR_ASSERT(bel_to_cell[bel.index] == nullptr);
 
         bel_to_cell[bel.index] = cell;
-        bel_carry[bel.index] = (cell->type == id_icestorm_lc && cell->lcInfo.carryEnable);
+        bel_carry[bel.index] = (cell->type == id_ICESTORM_LC && cell->lcInfo.carryEnable);
         cell->bel = bel;
         cell->belStrength = strength;
         refreshUiBel(bel);
@@ -810,15 +810,6 @@ struct Arch : BaseCtx
     void assignArchInfo();
     void assignCellInfo(CellInfo *cell);
 
-    IdString id_glb_buf_out;
-    IdString id_icestorm_lc, id_sb_io, id_sb_gb;
-    IdString id_cen, id_clk, id_sr;
-    IdString id_i0, id_i1, id_i2, id_i3;
-    IdString id_dff_en, id_carry_en, id_neg_clk;
-    IdString id_cin, id_cout;
-    IdString id_o, id_lo;
-    IdString id_icestorm_ram, id_rclk, id_wclk;
-
     // -------------------------------------------------
     BelPin getIOBSharingPLLPin(BelId pll, IdString pll_pin) const
     {
diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc
index 46f1f54f..bbddb7ee 100644
--- a/ice40/arch_place.cc
+++ b/ice40/arch_place.cc
@@ -91,7 +91,7 @@ bool Arch::isBelLocationValid(BelId bel) const
 
 bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
 {
-    if (cell->type == id_icestorm_lc) {
+    if (cell->type == id_ICESTORM_LC) {
         NPNR_ASSERT(getBelType(bel) == id_ICESTORM_LC);
 
         std::vector<const CellInfo *> bel_cells;
@@ -105,7 +105,7 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
 
         bel_cells.push_back(cell);
         return logicCellsCompatible(bel_cells);
-    } else if (cell->type == id_sb_io) {
+    } else if (cell->type == id_SB_IO) {
         // Do not allow placement of input SB_IOs on blocks where there a PLL is outputting to.
 
         // Find shared PLL by looking for driving bel siblings from D_IN_0
@@ -137,9 +137,9 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
             }
         }
         return getBelPackagePin(bel) != "";
-    } else if (cell->type == id_sb_gb) {
-        NPNR_ASSERT(cell->ports.at(id_glb_buf_out).net != nullptr);
-        const NetInfo *net = cell->ports.at(id_glb_buf_out).net;
+    } else if (cell->type == id_SB_GB) {
+        NPNR_ASSERT(cell->ports.at(id_GLOBAL_BUFFER_OUTPUT).net != nullptr);
+        const NetInfo *net = cell->ports.at(id_GLOBAL_BUFFER_OUTPUT).net;
         IdString glb_net = getWireName(getBelPinWire(bel, id_GLOBAL_BUFFER_OUTPUT));
         int glb_id = std::stoi(std::string("") + glb_net.str(this).back());
         if (net->is_reset && net->is_enable)
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index 60e8e699..7bdf82f0 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -57,6 +57,8 @@ slow_timings = None
 
 with open(args.constids) as f:
     for line in f:
+        if line.startswith("//"):
+            continue
         line = line.replace("(", " ")
         line = line.replace(")", " ")
         line = line.split()
diff --git a/ice40/constids.inc b/ice40/constids.inc
index f8a46a12..adcea7ad 100644
--- a/ice40/constids.inc
+++ b/ice40/constids.inc
@@ -1,3 +1,4 @@
+// pin and port names
 X(I0)
 X(I1)
 X(I2)
@@ -413,6 +414,7 @@ X(SLEEP)
 X(STANDBY)
 X(WREN)
 
+// cell and bel types
 X(ICESTORM_LC)
 X(ICESTORM_RAM)
 X(SB_IO)
@@ -428,3 +430,8 @@ X(IO_I3C)
 X(SB_LEDDA_IP)
 X(SB_RGBA_DRV)
 X(ICESTORM_SPRAM)
+
+// cell parameters
+X(DFF_ENABLE)
+X(CARRY_ENABLE)
+X(NEG_CLK)
diff --git a/ice40/delay.cc b/ice40/delay.cc
index a9607140..dd2a4969 100644
--- a/ice40/delay.cc
+++ b/ice40/delay.cc
@@ -192,7 +192,7 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
     auto driver_loc = getBelLocation(driver.cell->bel);
     auto sink_loc = getBelLocation(sink.cell->bel);
 
-    if (driver.port == id_cout) {
+    if (driver.port == id_COUT) {
         if (driver_loc.y == sink_loc.y)
             return 0;
         return 250;