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author | William D. Jones <thor0505@comcast.net> | 2021-02-02 01:41:44 -0500 |
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committer | gatecat <gatecat@ds0.me> | 2021-02-12 10:36:59 +0000 |
commit | da1b15d6f5a80653f7de848532227bfa58191998 (patch) | |
tree | 5aa4fb9bc32e113d2785388a8d49b431a3bad0e3 | |
parent | 8629d7b69285556cbf4edcb51916b5fb67693c02 (diff) | |
download | nextpnr-da1b15d6f5a80653f7de848532227bfa58191998.tar.gz nextpnr-da1b15d6f5a80653f7de848532227bfa58191998.tar.bz2 nextpnr-da1b15d6f5a80653f7de848532227bfa58191998.zip |
machxo2: Special-case left and right I/O wire names in ASCII generation.
-rw-r--r-- | machxo2/bitstream.cc | 36 |
1 files changed, 35 insertions, 1 deletions
diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc index 6f37e66b..a499d8a3 100644 --- a/machxo2/bitstream.cc +++ b/machxo2/bitstream.cc @@ -55,11 +55,45 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) std::string basename = ctx->tileInfo(wire)->wire_data[wire.index].name.get(); std::string prefix2 = basename.substr(0, 2); std::string prefix7 = basename.substr(0, 7); + int max_col = ctx->chip_info->width - 1; + + // Handle MachXO2's wonderful naming quirks for wires in left/right tiles, whose + // relative coords push them outside the bounds of the chip. + auto is_pio_wire = [](std::string name) { + return ( + name.find("DI") != std::string::npos || + name.find("JDI") != std::string::npos || + name.find("PADD") != std::string::npos || + name.find("INDD") != std::string::npos || + name.find("IOLDO") != std::string::npos || + name.find("IOLTO") != std::string::npos || + name.find("JCE") != std::string::npos || + name.find("JCLK") != std::string::npos || + name.find("JLSR") != std::string::npos || + name.find("JONEG") != std::string::npos || + name.find("JOPOS") != std::string::npos || + name.find("JTS") != std::string::npos || + name.find("JIN") != std::string::npos || + name.find("JIP") != std::string::npos || + // Connections to global mux + name.find("JINCK") != std::string::npos + ); + }; + if (prefix2 == "G_" || prefix2 == "L_" || prefix2 == "R_" || prefix2 == "U_" || prefix2 == "D_" || prefix7 == "BRANCH_") return basename; - if (loc == wire.location) + if (loc == wire.location) { + // TODO: JINCK is not currently handled by this. + if(is_pio_wire(basename)) { + if(wire.location.x == 0) + return "W1_" + basename; + else if(wire.location.x == max_col) + return "E1_" + basename; + } return basename; + } + std::string rel_prefix; if (wire.location.y < loc.y) rel_prefix += "N" + std::to_string(loc.y - wire.location.y); |