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authorDavid Shah <davey1576@gmail.com>2018-06-16 11:17:17 +0200
committerDavid Shah <davey1576@gmail.com>2018-06-16 14:44:10 +0200
commitc9a784ec0cca9d1d39386e1e3c3dc5ec0da9c03e (patch)
tree47d12ab2dfc9106a5a0c74b7e1851fc7d4f201d7
parent04f1d7516a2001087101430c0561e31a448e0893 (diff)
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ice40: Include RAM init data in bitstream
Signed-off-by: David Shah <davey1576@gmail.com>
-rw-r--r--ice40/bitstream.cc40
1 files changed, 40 insertions, 0 deletions
diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc
index 0790a919..fa8e444d 100644
--- a/ice40/bitstream.cc
+++ b/ice40/bitstream.cc
@@ -77,6 +77,18 @@ int get_param_or_def(const CellInfo *cell, const std::string &param,
return defval;
}
+std::string get_param_str_or_def(const CellInfo *cell, const std::string &param,
+ std::string defval = "")
+{
+ auto found = cell->params.find(param);
+ if (found != cell->params.end())
+ return found->second;
+ else
+ return defval;
+}
+
+char get_hexdigit(int i) { return std::string("0123456789ABCDEF").at(i); }
+
void write_asc(const Design &design, std::ostream &out)
{
const Chip &chip = design.chip;
@@ -357,6 +369,34 @@ void write_asc(const Design &design, std::ostream &out)
out << std::endl;
}
}
+
+ // Write RAM init data
+ for (auto cell : design.cells) {
+ if (cell.second->bel != BelId()) {
+ if (cell.second->type == "ICESTORM_RAM") {
+ const BelInfoPOD &beli = ci.bel_data[cell.second->bel.index];
+ int x = beli.x, y = beli.y;
+ out << ".ram_data " << x << " " << y << std::endl;
+ for (int w = 0; w < 16; w++) {
+ std::vector<bool> bits(256);
+ std::string init = get_param_str_or_def(
+ cell.second,
+ std::string("INIT_") + get_hexdigit(w));
+ for (int i = 0; i < init.size(); i++) {
+ bool val = (init.at((init.size() - 1) - i) == '1');
+ bits.at(i) = val;
+ }
+ for (int i = 0; i < bits.size(); i += 4) {
+ int c = bits.at(i) + (bits.at(i + 1) << 1) +
+ (bits.at(i + 2) << 2) + (bits.at(i + 3) << 3);
+ out << get_hexdigit(c);
+ }
+ out << std::endl;
+ }
+ out << std::endl;
+ }
+ }
+ }
}
NEXTPNR_NAMESPACE_END