Merge branch 'master' into mmaped_chipdb

4 files changed, 42 insertions, 8 deletions

diff --git a/common/timing.cc b/common/timing.cc
index 13f0e07b..64dcdf71 100644
--- a/common/timing.cc
+++ b/common/timing.cc
@@ -930,8 +930,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
         unsigned bar_width = 60;
         auto min_slack = slack_histogram.begin()->first;
         auto max_slack = slack_histogram.rbegin()->first;
-        auto bin_size = std::max(1u, (max_slack - min_slack) / num_bins);
-        num_bins = std::min((max_slack - min_slack) / bin_size, num_bins) + 1;
+        auto bin_size = std::max<unsigned>(1, ceil((max_slack - min_slack + 1) / float(num_bins)));
         std::vector<unsigned> bins(num_bins);
         unsigned max_freq = 0;
         for (const auto &i : slack_histogram) {
diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 75949b2f..23cdea3b 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -427,7 +427,28 @@ BelId Arch::getBelByLocation(Loc loc) const
 
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
-    return (240 - 20 * args.speed) * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
+    auto est_location = [&](WireId w) -> std::pair<int16_t, int16_t> {
+        if (w.location.x == 0 && w.location.y == 0) {
+            // Global wires
+            const auto &wire = locInfo(w)->wire_data[w.index];
+            // Use location of first downhill bel or pip, if available
+            if (wire.num_bel_pins > 0) {
+                return std::make_pair(wire.bel_pins[0].rel_bel_loc.x, wire.bel_pins[0].rel_bel_loc.y);
+            } else if (wire.num_downhill > 0) {
+                return std::make_pair(wire.pips_downhill[0].rel_loc.x, wire.pips_downhill[0].rel_loc.y);
+            } else if (wire.num_uphill > 0) {
+                return std::make_pair(wire.pips_uphill[0].rel_loc.x, wire.pips_uphill[0].rel_loc.y);
+            } else {
+                return std::make_pair<int16_t, int16_t>(0, 0);
+            }
+        } else {
+            return std::make_pair(w.location.x, w.location.y);
+        }
+    };
+
+    auto src_loc = est_location(src), dst_loc = est_location(dst);
+
+    return (240 - 20 * args.speed) * (abs(src_loc.first - dst_loc.first) + abs(src_loc.second - dst_loc.second));
 }
 
 delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
diff --git a/ecp5/family.cmake b/ecp5/family.cmake
index 06dc6761..799851b2 100644
--- a/ecp5/family.cmake
+++ b/ecp5/family.cmake
@@ -6,12 +6,19 @@ if (NOT EXTERNAL_CHIPDB)
         set(TRELLIS_ROOT "/usr/local/share/trellis")
     endif()
 
-    file(GLOB found_pytrellis ${TRELLIS_ROOT}/libtrellis/pytrellis.*)
+    file(GLOB found_pytrellis ${TRELLIS_ROOT}/libtrellis/pytrellis.*
+                              /usr/lib/pytrellis.*
+                              /usr/lib64/pytrellis.*
+                              /usr/lib/trellis/pytrellis.*
+                              /usr/lib64/trellis/pytrellis.*)
 
     if ("${found_pytrellis}" STREQUAL "")
-        message(FATAL_ERROR "failed to find pytrellis library in ${TRELLIS_ROOT}/libtrellis/")
+        message(FATAL_ERROR "failed to locate pytrellis library!")
     endif()
 
+    list(GET found_pytrellis 0 PYTRELLIS_LIB)
+    get_filename_component(PYTRELLIS_LIBDIR ${PYTRELLIS_LIB} DIRECTORY)
+
     set(DB_PY ${CMAKE_CURRENT_SOURCE_DIR}/ecp5/trellis_import.py)
 
     file(MAKE_DIRECTORY ecp5/chipdbs/)
@@ -20,9 +27,9 @@ if (NOT EXTERNAL_CHIPDB)
     target_include_directories(ecp5_chipdb PRIVATE ${family}/)
 
     if (CMAKE_HOST_WIN32)
-    set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=\"${TRELLIS_ROOT}/libtrellis\;${TRELLIS_ROOT}/util/common\;${TRELLIS_ROOT}/timing/util\"")
+    set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=\"${PYTRELLIS_LIBDIR}\;${TRELLIS_ROOT}/util/common\;${TRELLIS_ROOT}/timing/util\"")
     else()
-    set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=${TRELLIS_ROOT}/libtrellis:${TRELLIS_ROOT}/util/common:${TRELLIS_ROOT}/timing/util")
+    set(ENV_CMD ${CMAKE_COMMAND} -E env "PYTHONPATH=${PYTRELLIS_LIBDIR}\:${TRELLIS_ROOT}/util/common:${TRELLIS_ROOT}/timing/util")
     endif()
 
     if (MSVC)
diff --git a/ice40/pack.cc b/ice40/pack.cc
index a86083b6..c22c4e8c 100644
--- a/ice40/pack.cc
+++ b/ice40/pack.cc
@@ -770,6 +770,8 @@ static void place_plls(Context *ctx)
                       io_cell->name.c_str(ctx));
         if (pll_used_bels.count(found_bel)) {
             CellInfo *conflict_cell = pll_used_bels.at(found_bel);
+            if (conflict_cell == ci)
+                continue;
             log_error("PLL '%s' PACKAGEPIN forces it to BEL %s but BEL is already assigned to PLL '%s'\n",
                       ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx), conflict_cell->name.c_str(ctx));
         }
@@ -1063,7 +1065,12 @@ static void pack_special(Context *ctx)
                     create_ice_cell(ctx, ctx->id("ICESTORM_PLL"), ci->name.str(ctx) + "_PLL");
             packed->attrs[ctx->id("TYPE")] = ci->type.str(ctx);
             packed_cells.insert(ci->name);
-
+            if (!is_sb_pll40_dual(ctx, ci)) {
+                // Remove second output, so a buffer isn't created for it, for these
+                // cell types with only one output
+                packed->ports.erase(ctx->id("PLLOUT_B"));
+                packed->ports.erase(ctx->id("PLLOUT_B_GLOBAL"));
+            }
             for (auto attr : ci->attrs)
                 packed->attrs[attr.first] = attr.second;
             for (auto param : ci->params)