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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2018-08-08 08:31:08 -0700 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2018-08-08 08:31:08 -0700 |
| commit | 91023d2a0e6c4d15b640f9c913565b8298f0a19c (patch) | |
| tree | 782f8d3c4ee441fb1afb8b340025e90c6a08246e | |
| parent | 90e3db324eb016b6c5ae4168db6ac00f65c2af4e (diff) | |
| download | nextpnr-91023d2a0e6c4d15b640f9c913565b8298f0a19c.tar.gz nextpnr-91023d2a0e6c4d15b640f9c913565b8298f0a19c.tar.bz2 nextpnr-91023d2a0e6c4d15b640f9c913565b8298f0a19c.zip | |
Leave comment behind about removing false paths
| -rw-r--r-- | common/timing.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/common/timing.cc b/common/timing.cc index a3b5235a..c1be083d 100644 --- a/common/timing.cc +++ b/common/timing.cc @@ -92,7 +92,7 @@ struct Timing topographical_order.emplace_back(o->net); net_data.emplace(o->net, TimingData{clkToQ.maxDelay()}); } else { - // TODO: how to process ignore here + // TODO(eddieh): Generated clocks and ignored ports are currently added into the ordering as if it was a regular timing start point in order to enable the full topographical order to be computed, however these false nets (and their downstream paths) should not be in the final ordering if (portClass == TMG_STARTPOINT || portClass == TMG_GEN_CLOCK || portClass == TMG_IGNORE) { topographical_order.emplace_back(o->net); net_data.emplace(o->net, TimingData{}); |