Add iCE40 blinky example

Signed-off-by: Clifford Wolf <clifford@clifford.at>

3 files changed, 152 insertions, 0 deletions

diff --git a/ice40/blinky.v b/ice40/blinky.v
new file mode 100644
index 00000000..6b97c5a9
--- /dev/null
+++ b/ice40/blinky.v
@@ -0,0 +1,57 @@
+module blinky (
+	input  clk_pin,
+	output led1_pin,
+	output led2_pin,
+	output led3_pin,
+	output led4_pin,
+	output led5_pin
+);
+	wire clk, led1, led2, led3, led4, led5;
+
+	SB_IO #(
+		.PIN_TYPE(6'b 0110_01),
+		.PULLUP(1'b0),
+		.NEG_TRIGGER(1'b0)
+	) led_iob [4:0] (
+		.PACKAGE_PIN({led1_pin, led2_pin, led3_pin, led4_pin, led5_pin}),
+		.LATCH_INPUT_VALUE(),
+		.CLOCK_ENABLE(),
+		.INPUT_CLK(),
+		.OUTPUT_CLK(),
+		.OUTPUT_ENABLE(),
+		.D_OUT_0({led1, led2, led3, led4, led5}),
+		.D_OUT_1(),
+		.D_IN_0(),
+		.D_IN_1()
+	);
+
+	SB_IO #(
+		.PIN_TYPE(6'b 0000_01),
+		.PULLUP(1'b0),
+		.NEG_TRIGGER(1'b0)
+	) clk_iob (
+		.PACKAGE_PIN(clk_pin),
+		.LATCH_INPUT_VALUE(),
+		.CLOCK_ENABLE(),
+		.INPUT_CLK(),
+		.OUTPUT_CLK(),
+		.OUTPUT_ENABLE(),
+		.D_OUT_0(),
+		.D_OUT_1(),
+		.D_IN_0(clk),
+		.D_IN_1()
+	);
+
+	localparam BITS = 5;
+	localparam LOG2DELAY = 22;
+
+	reg [BITS+LOG2DELAY-1:0] counter = 0;
+	reg [BITS-1:0] outcnt;
+
+	always @(posedge clk) begin
+		counter <= counter + 1;
+		outcnt <= counter >> LOG2DELAY;
+	end
+
+	assign {led1, led2, led3, led4, led5} = outcnt ^ (outcnt >> 1);
+endmodule
diff --git a/ice40/blinky.ys b/ice40/blinky.ys
new file mode 100644
index 00000000..9c51dc88
--- /dev/null
+++ b/ice40/blinky.ys
@@ -0,0 +1,9 @@
+read_verilog blinky.v
+read_verilog -lib +/ice40/cells_sim.v
+synth -top blinky
+abc -lut 4
+techmap -map blinky_map.v
+splitnets
+opt_clean
+stat
+write_json blinky.json
diff --git a/ice40/blinky_map.v b/ice40/blinky_map.v
new file mode 100644
index 00000000..fc0e7201
--- /dev/null
+++ b/ice40/blinky_map.v
@@ -0,0 +1,86 @@
+module \$_DFF_P_ (input D, C, output Q);
+	ICESTORM_LC #(
+		.LUT_INIT(1),
+		.NEG_CLK(0),
+		.CARRY_ENABLE(0),
+		.DFF_ENABLE(1),
+		.SET_NORESET(0),
+		.ASYNC_SR(0)
+	) _TECHMAP_REPLACE_ (
+		.I0(D),
+		.CLK(C),
+		.O(Q),
+
+		.I1(),
+		.I2(),
+		.I3(),
+		.CIN(),
+		.CEN(),
+		.SR(),
+		.LO(),
+		.COUT()
+	);
+endmodule
+
+module \$lut (A, Y);
+	parameter WIDTH = 0;
+	parameter LUT = 0;
+
+	input [WIDTH-1:0] A;
+	output Y;
+
+	generate
+		if (WIDTH == 1) begin
+			ICESTORM_LC #(
+				.LUT_INIT(LUT),
+				.NEG_CLK(0),
+				.CARRY_ENABLE(0),
+				.DFF_ENABLE(0),
+				.SET_NORESET(0),
+				.ASYNC_SR(0)
+			) _TECHMAP_REPLACE_ (
+				.I0(A[0]), .I1(), .I2(), .I3(), .O(Y),
+				.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
+			);
+		end
+		if (WIDTH == 2) begin
+			ICESTORM_LC #(
+				.LUT_INIT(LUT),
+				.NEG_CLK(0),
+				.CARRY_ENABLE(0),
+				.DFF_ENABLE(0),
+				.SET_NORESET(0),
+				.ASYNC_SR(0)
+			) _TECHMAP_REPLACE_ (
+				.I0(A[0]), .I1(A[1]), .I2(), .I3(), .O(Y),
+				.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
+			);
+		end
+		if (WIDTH == 3) begin
+			ICESTORM_LC #(
+				.LUT_INIT(LUT),
+				.NEG_CLK(0),
+				.CARRY_ENABLE(0),
+				.DFF_ENABLE(0),
+				.SET_NORESET(0),
+				.ASYNC_SR(0)
+			) _TECHMAP_REPLACE_ (
+				.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(), .O(Y),
+				.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
+			);
+		end
+		if (WIDTH == 4) begin
+			ICESTORM_LC #(
+				.LUT_INIT(LUT),
+				.NEG_CLK(0),
+				.CARRY_ENABLE(0),
+				.DFF_ENABLE(0),
+				.SET_NORESET(0),
+				.ASYNC_SR(0)
+			) _TECHMAP_REPLACE_ (
+				.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .O(Y),
+				.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
+			);
+		end
+	endgenerate
+endmodule