interchange: Don't error out on missing cell ports

This is required for LUTRAM support, as the upper address bits of
RAMD64E etc are missing for shallower primitives.

Signed-off-by: gatecat <gatecat@ds0.me>

2 files changed, 3 insertions, 2 deletions

diff --git a/fpga_interchange/site_arch.cc b/fpga_interchange/site_arch.cc
index 4438193b..ed2f6c8d 100644
--- a/fpga_interchange/site_arch.cc
+++ b/fpga_interchange/site_arch.cc
@@ -136,6 +136,8 @@ SiteArch::SiteArch(const SiteInformation *site_info) : ctx(site_info->ctx), site
     bool have_vcc_pins = false;
     for (CellInfo *cell : site_info->cells_in_site) {
         for (const auto &pin_pair : cell->cell_bel_pins) {
+            if (!cell->ports.count(pin_pair.first))
+                continue;
             const PortInfo &port = cell->ports.at(pin_pair.first);
             if (port.net != nullptr) {
                 nets.emplace(port.net, SiteNetInfo{port.net});
diff --git a/fpga_interchange/site_router.cc b/fpga_interchange/site_router.cc
index f4d65958..69bd366f 100644
--- a/fpga_interchange/site_router.cc
+++ b/fpga_interchange/site_router.cc
@@ -59,8 +59,7 @@ bool check_initial_wires(const Context *ctx, SiteInformation *site_info)
         BelId bel = cell->bel;
         for (const auto &pin_pair : cell->cell_bel_pins) {
             if (!cell->ports.count(pin_pair.first))
-                log_error("Cell %s:%s is missing expected port %s\n", ctx->nameOf(cell), cell->type.c_str(ctx),
-                          pin_pair.first.c_str(ctx));
+                continue;
             const PortInfo &port = cell->ports.at(pin_pair.first);
             NPNR_ASSERT(port.net != nullptr);